| Message ID | 20240909-fix_clk-v3-0-a6d8f6333c04@amlogic.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: meson: Fix an issue with inaccurate hifi_pll frequency | expand |
Applied to clk-meson (clk-meson-next), thanks!
[1/3] clk: meson: Support PLL with fixed fractional denominators
https://github.com/BayLibre/clk-meson/commit/1287bdc8c6db
[2/3] clk: meson: c3: pll: fix frac maximum value for hifi_pll
https://github.com/BayLibre/clk-meson/commit/d4bc8851da59
[3/3] clk: meson: s4: pll: fix frac maximum value for hifi_pll
https://github.com/BayLibre/clk-meson/commit/0ef513560b53
Best regards,
--
Jerome
Some PLLS with fractional multipliers have fractional denominators with fixed values, instead of the previous "(1 << pll-> frc.width)". The hifi_pll for both C3 and S4 supports a fractional multiplier and has a fixed fractional denominator of "100000". Here are the results of the C3-based command tests (already defined CLOCK_ALLOW_WRITE_DEBUGFS): * echo 491520000 > /sys/kernel/debug/clk/hifi_pll/clk_rate * cat /sys/kernel/debug/clk/hifi_pll/clk_rate 491520000 * echo 1 > /sys/kernel/debug/clk/hifi_pll/clk_prepare_enable * cat /sys/kernel/debug/meson-clk-msr/clks/hifi_pll_clk 491515625 +/-15625Hz * devmem 0xfe008100 32 0xD00304A3 * devmem 0xfe008104 32 0x00014820 Based on the register information read above, it can be obtained: m = 0xA3 = 0d163; n = 0x1 = 0d1 frac = 0x14820 = 0d84000 od = 0x3 = 0d3 hifi_pll calculates the output frequency: calc_rate = xtal_rate / n * (m + (frac / frac_max)) >> od; calc_rate = 24000000 / 1 * (163 + (84000 / 100000)) >> 3; calc_rate = 491520000 clk_rate, msr_rate, and calc_rate all match. The test and calculation results of S4 are consistent with those of C3, which will not be repeated here. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> --- Changes in v3: - Drop the call to unlikely(). - Link to v2: https://lore.kernel.org/r/20240906-fix_clk-v2-0-7a3941eb2cdf@amlogic.com Changes in v2: - Added frac_max to the pll parameter instead of flag. - frac_max is added to hifi_pll for C3 and S4. - Link to v1: https://lore.kernel.org/r/20240906-fix_clk-v1-0-2977ef0d72e7@amlogic.com --- Chuan Liu (3): clk: meson: Support PLL with fixed fractional denominators clk: meson: c3: pll: fix frac maximum value for hifi_pll clk: meson: s4: pll: fix frac maximum value for hifi_pll drivers/clk/meson/c3-pll.c | 1 + drivers/clk/meson/clk-pll.c | 8 +++++--- drivers/clk/meson/clk-pll.h | 1 + drivers/clk/meson/s4-pll.c | 1 + 4 files changed, 8 insertions(+), 3 deletions(-) --- base-commit: 80344f4c1a1edec507a20adca476af84ea58cd4c change-id: 20240904-fix_clk-668f7a1a2b16 Best regards,