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[88.10.59.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cc01cae3asm5516055e9.0.2024.09.09.21.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 21:40:25 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de, yangshiji66@outlook.com, linux-kernel@vger.kernel.org Subject: [PATCH 0/3] clk: ralink: mtmips: some fixes and sdhc clock support Date: Tue, 10 Sep 2024 06:40:21 +0200 Message-Id: <20240910044024.120009-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Stephen, The following first two patches contains several fixes for having a correct clock plan from the beggining in old ralink SoCs that could not be tested when the driver was mainlained due to the lack of users. Now some issues have been reported regarding RT3883 in openWRT[0] so I am addressing and fixing them here. The last patch adds new clocks to properly support sdhc 48 MHz clock for Mt7620, Mt7628 and Mt7688 SoCs. OpenWRT people updated to use SDHC upstream driver so they were forced to add a not desired fixed dts node[1] to make it works. The correct thing to do is just support it in mtmips driver. Hence we have add it here. Thanks in advance for your time. Best regards, Sergio Paracuellos [0]: https://github.com/openwrt/openwrt/issues/16054 [1]: https://github.com/openwrt/openwrt/pull/15896/files Sergio Paracuellos (3): clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883 clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688 drivers/clk/ralink/clk-mtmips.c | 56 ++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 15 deletions(-)