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[89.38.97.199]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99a80dc5easm85654466b.170.2024.10.10.05.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 05:46:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Sam Shih , Daniel Golle , Bartosz Golaszewski Cc: Yassine Oudjana , Yassine Oudjana , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 0/2] MediaTek MT6735 main clock and reset drivers Date: Thu, 10 Oct 2024 15:45:24 +0300 Message-ID: <20241010124529.78460-1-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.46.2 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yassine Oudjana These patches are part of a larger effort to support the MT6735 SoC family in mainline Linux. More patches (unsent or sent and pending review or revision) can be found here[1]. This series adds support for the main clock and reset controllers on the Mediatek MT6735 SoC: - apmixedsys (global PLLs) - topckgen (global divisors and muxes) - infracfg (gates and resets for infrastructure blocks) - pericfg (gates and resets for peripherals) MT6735 has other more specialized clock/reset controllers, support for which is not included in this series: - mfgcfg (GPU) - imgsys (camera) - mmsys (display) - vdecsys (video decoder) - vencsys (video encoder) - audsys (audio) Changes since v4: - Follow naming convention for DT bindings - Add reset map Changes since v3: - Squash DT binding patches. - Use mtk_clk_simple_probe/mtk_clk_simple_remove for topckgen. - Add MODULE_DEVICE_TABLE in all drivers. Changes since v2: - Add "CLK_" prefix to infracfg and pericfg clock definitions to avoid possible clashes with reset bindings. - Replace "_RST" suffix with "RST_" prefix to maintain consistency with clock bindings. - Use macros to define clocks. - Abandon mtk_clk_simple_probe/mtk_clk_simple_remove in favor of custom functions in apmixedsys and topckgen drivers for the time being. - Capitalize T in MediaTek in MODULE_DESCRIPTION. Changes since v1: - Rebase on some pending patches. - Move common clock improvements to a separate series. - Use mtk_clk_simple_probe/remove after making them support several clock types in said series. - Combine all 4 drivers into one patch, and use one Kconfig symbol for all following a conversation seen on a different series[2]. - Correct APLL2 registers in apmixedsys driver (were offset backwards by 0x4). - Make irtx clock name lower case to match the other clocks. [1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging [2] https://lore.kernel.org/linux-mediatek/CAGXv+5H4gF5GXzfk8mjkG4Kry8uCs1CQbKoViBuc9LC+XdHH=A@mail.gmail.com/ Yassine Oudjana (2): dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers .../bindings/clock/mediatek,apmixedsys.yaml | 4 +- .../bindings/clock/mediatek,infracfg.yaml | 8 +- .../bindings/clock/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,topckgen.yaml | 4 +- MAINTAINERS | 16 + drivers/clk/mediatek/Kconfig | 9 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 138 ++++++ drivers/clk/mediatek/clk-mt6735-infracfg.c | 107 +++++ drivers/clk/mediatek/clk-mt6735-pericfg.c | 124 ++++++ drivers/clk/mediatek/clk-mt6735-topckgen.c | 394 ++++++++++++++++++ .../clock/mediatek,mt6735-apmixedsys.h | 16 + .../clock/mediatek,mt6735-infracfg.h | 25 ++ .../clock/mediatek,mt6735-pericfg.h | 37 ++ .../clock/mediatek,mt6735-topckgen.h | 79 ++++ .../reset/mediatek,mt6735-infracfg.h | 27 ++ .../reset/mediatek,mt6735-pericfg.h | 31 ++ 17 files changed, 1016 insertions(+), 5 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h