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Date: Fri, 11 Oct 2024 00:28:30 +0530 Message-ID: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIANYjCGcC/y3NwQrCMBCE4Vcpe3YhjQkRX0U8hGZq99AYs20RS t/doB6/Ofyzk6IKlK7dThWbqDxzgz91NEwxP8CSmska63rTG9Z4CcEXnmfeHFcocuISl2GCsrP h7BNGb6OhligVo7y/+dv954rX2l6W/3gcHyMyPRmDAAAA X-Change-ID: 20241010-sa8775p-mm-v4-resend-patches-42735def52a0 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski CC: , , , , Taniya Das , Krzysztof Kozlowski , "Krzysztof Kozlowski" , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sqsOdff03max4xpZJeyJgbD4xjfq99kA X-Proofpoint-GUID: sqsOdff03max4xpZJeyJgbD4xjfq99kA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100125 [v5] Rebased the device tree patch to add clock controller nodes. [v4] Changes in [v4] compared to [v3] Videocc: Update the mvs0/mvs1 gdsc to use HW_CTRL_TRIGGER [Konrad and Qualcomm internal discussions] Camcc: Add new clock to the clock tree. Change the patch order for 'Update sleep_clk frequency to 32000 on SA8775P' [Krzysztof] Changes in [v3] compared to [v2]: Update the qcom_cc_really_probe() to use &pdev->dev, for the CAMCC, DISPCC & VIDEOCC drivers. [v2] https://lore.kernel.org/all/20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com/ Changes in [v2] compared to [v1]: [PATCH 1/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 3/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 5/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 7/8]: Split updating sleep_clk frequency to separate patch [PATCH 8/8]: Newly added to update sleep_clk frequency to 32000 These multimedia clock controller and device tree patches are split from the below [v1] series. [v1] https://lore.kernel.org/all/20240531090249.10293-1-quic_tdas@quicinc.com/ Signed-off-by: Taniya Das --- Taniya Das (8): dt-bindings: clock: qcom: Add SA8775P video clock controller clk: qcom: Add support for Video clock controller on SA8775P dt-bindings: clock: qcom: Add SA8775P camera clock controller clk: qcom: Add support for Camera Clock Controller on SA8775P dt-bindings: clock: qcom: Add SA8775P display clock controllers clk: qcom: Add support for Display clock Controllers on SA8775P arm64: dts: qcom: Update sleep_clk frequency to 32000 on SA8775P arm64: dts: qcom: Add support for multimedia clock controllers .../bindings/clock/qcom,sa8775p-camcc.yaml | 62 + .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 + .../bindings/clock/qcom,sa8775p-videocc.yaml | 62 + arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 + drivers/clk/qcom/Kconfig | 31 + drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/camcc-sa8775p.c | 1868 ++++++++++++++++++++ drivers/clk/qcom/dispcc0-sa8775p.c | 1481 ++++++++++++++++ drivers/clk/qcom/dispcc1-sa8775p.c | 1481 ++++++++++++++++ drivers/clk/qcom/videocc-sa8775p.c | 576 ++++++ include/dt-bindings/clock/qcom,sa8775p-camcc.h | 108 ++ include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 + include/dt-bindings/clock/qcom,sa8775p-videocc.h | 47 + 14 files changed, 5943 insertions(+), 1 deletion(-) --- base-commit: 0cca97bf23640ff68a6e8a74e9b6659fdc27f48c change-id: 20241010-sa8775p-mm-v4-resend-patches-42735def52a0 Best regards,