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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4316f57f89fsm29794305e9.16.2024.10.20.10.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 10:50:48 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/3] clk: samsung: Introduce Exynos8895 clock driver Date: Sun, 20 Oct 2024 20:48:22 +0300 Message-ID: <20241020174825.375096-1-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hey folks, This patchset adds initial clock driver support for Exynos8895 SoC, which allows clocking peripherals like MCT, serial buses, MMC, UFS and PCIE. As platform support grows in the future, other blocks like APM will be added. Support for the following clock management unit blocks is implemented in this patchset: - CMU_TOP - CMU_FSYS0/1 - CMU_PERIC0/1 - CMU_PERIS Ivaylo Ivanov (3): dt-bindings: clock: Add Exynos8895 SoC CMU bindings clk: samsung: clk-pll: Add support for pll_{1051x,1052x} clk: samsung: Introduce Exynos8895 clock driver .../clock/samsung,exynos8895-clock.yaml | 243 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos8895.c | 2803 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 2 + drivers/clk/samsung/clk-pll.h | 2 + .../dt-bindings/clock/samsung,exynos8895.h | 535 ++++ 6 files changed, 3586 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynos8895.c create mode 100644 include/dt-bindings/clock/samsung,exynos8895.h