Message ID | 20241021121618.151079-1-y.oudjana@protonmail.com (mailing list archive) |
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Mon, 21 Oct 2024 05:16:29 -0700 (PDT) Received: from zenbook.agu.edu.tr ([95.183.227.34]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a912d6ee6sm197068966b.4.2024.10.21.05.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 05:16:28 -0700 (PDT) From: Yassine Oudjana <yassine.oudjana@gmail.com> X-Google-Original-From: Yassine Oudjana <y.oudjana@protonmail.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Philipp Zabel <p.zabel@pengutronix.de>, Lukas Bulwahn <lukas.bulwahn@redhat.com>, Daniel Golle <daniel@makrotopia.org>, Sam Shih <sam.shih@mediatek.com> Cc: Yassine Oudjana <y.oudjana@protonmail.com>, Yassine Oudjana <yassine.oudjana@gmail.com>, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/2] MediaTek MT6735 syscon clock/reset controller support Date: Mon, 21 Oct 2024 15:16:14 +0300 Message-ID: <20241021121618.151079-1-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.47.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: <linux-clk.vger.kernel.org> List-Subscribe: <mailto:linux-clk+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-clk+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
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MediaTek MT6735 syscon clock/reset controller support
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From: Yassine Oudjana <y.oudjana@protonmail.com> These patches are part of a larger effort to support the MT6735 SoC family in mainline Linux. More patches can found here[1]. This series adds support for clocks and resets of the following blocks: - IMGSYS (Camera) - MFGCFG (GPU) - VDECSYS (Video decoder) - VENCSYS (Video encoder, also has JPEG codec clocks) [1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging Yassine Oudjana (2): dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers .../bindings/clock/mediatek,syscon.yaml | 4 + MAINTAINERS | 10 +++ drivers/clk/mediatek/Kconfig | 32 ++++++++ drivers/clk/mediatek/Makefile | 4 + drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 +++++++++++++ drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 ++++++++++++++ drivers/clk/mediatek/clk-mt6735-vdecsys.c | 81 +++++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 ++++++++++++ .../clock/mediatek,mt6735-imgsys.h | 15 ++++ .../clock/mediatek,mt6735-mfgcfg.h | 8 ++ .../clock/mediatek,mt6735-vdecsys.h | 9 +++ .../clock/mediatek,mt6735-vencsys.h | 11 +++ .../reset/mediatek,mt6735-mfgcfg.h | 9 +++ .../reset/mediatek,mt6735-vdecsys.h | 10 +++ 14 files changed, 364 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h