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Wed, 18 Dec 2024 06:20:49 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 0/5] Add SYS and GIC clock entries for RZ/V2H(P) SoC Date: Wed, 18 Dec 2024 14:20:40 +0000 Message-ID: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series adds support for clock and reset entries for GIC and SYS, along with some cleanup and fixes to the CPG family driver. Cheers, Prabhakar Lad Prabhakar (5): clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r9a09g057: Add clock and reset entries for GIC drivers/clk/renesas/r9a09g057-cpg.c | 5 +++++ drivers/clk/renesas/rzv2h-cpg.c | 15 +++++++++++---- drivers/clk/renesas/rzv2h-cpg.h | 8 ++++---- 3 files changed, 20 insertions(+), 8 deletions(-)