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Mon, 14 Apr 2025 09:00:59 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 14 Apr 2025 02:00:56 -0700 From: Taniya Das Subject: [PATCH 0/2] clk: qcom: gcc: Update the force_mem_core for UFS ICE Date: Mon, 14 Apr 2025 14:30:39 +0530 Message-ID: <20250414-gcc_ufs_mem_core-v1-0-67b5529b9b5d@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIALfO/GcC/x3MQQqAIBBA0avIrBPKDKOrREhNU83CDKUIxLsnL d/i/wSRAlOEQSQI9HBkfxY0lQA85nMnyWsxqFp1tW603BHtvUXryFn0gaRZFtXPbacMIZTsCrT x+y/HKecPPDP5QmIAAAA= X-Change-ID: 20250414-gcc_ufs_mem_core-7bb28a3527ec To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SXp6c7EGbrymVrEx3pwBIbjwd3aSra1T X-Proofpoint-ORIG-GUID: SXp6c7EGbrymVrEx3pwBIbjwd3aSra1T X-Authority-Analysis: v=2.4 cv=Cve/cm4D c=1 sm=1 tr=0 ts=67fccecc cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=M75u7Tp2MPcvN9VRiHUA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_02,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=647 mlxscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140064 The MCQ feature of UFS requires the both UFS ice and UFS phy axi clocks to have the force_mem_core bit set to allow retention after power collapse. Signed-off-by: Taniya Das --- Taniya Das (2): clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks drivers/clk/qcom/gcc-sm8650.c | 2 ++ drivers/clk/qcom/gcc-sm8750.c | 3 ++- drivers/clk/qcom/gcc-x1e80100.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) --- base-commit: 01c6df60d5d4ae00cd5c1648818744838bba7763 change-id: 20250414-gcc_ufs_mem_core-7bb28a3527ec Best regards,