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Sat, 9 Mar 2024 09:02:18 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::8615:efe2:7c8e:2041]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::8615:efe2:7c8e:2041%3]) with mapi id 15.20.7362.030; Sat, 9 Mar 2024 09:02:17 +0000 From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chao Wei , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto Cc: Jisheng Zhang , Liu Gui , Jingbao Qiu , dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v9 0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Date: Sat, 9 Mar 2024 17:01:21 +0800 Message-ID: X-Mailer: git-send-email 2.44.0 X-TMN: [em0rheyqiWm4b20DP98OoLbeYI6QcF0VDrHxlEQGomk=] X-ClientProxiedBy: TYWP286CA0029.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:262::17) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20240309090122.927241-1-inochiama@outlook.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|MW5PR20MB4260:EE_ X-MS-Office365-Filtering-Correlation-Id: 925f8e54-bb94-4fbe-11f6-08dc40179ebb X-Microsoft-Antispam: BCL:0; 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Changed from v8: 1. improve code. 2. remove default config in Kconfig. 3. merge patch 2-4 of v8 into one. Changed from v7: 1. fix unused variables warnings in patch 3 of v7 2. fix wrong pointer type in patch 3 of v7 3. move the clk_disp_vip_parents variable to the patch 5 to avoid warning Changed from v6: 1. fix dead lock when setting rate. 2. split the driver patch into several patch for easy reading. Changed from v5: 1. rebased to mainline master tree 2. add SG2000 clock support. 3. fix document link Changed from v4: 1. improve code for patch 2 2. remove the already applied bindings https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v3: 1. improve comment of patch 3 2. cleanup the include of patch 2 Changed from v2: 1. remove clock-names from bindings. 2. remove clock-frequency node of DT from previous patch. 3. change some unused clock to bypass mode to avoid unlockable PLL. Changed from v1: 1. fix license issues. Inochi Amaoto (6): dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC clk: sophgo: Add clock support for CV1800 SoC clk: sophgo: Add clock support for CV1810 SoC clk: sophgo: Add clock support for SG2000 SoC riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC .../bindings/clock/sophgo,cv1800-clk.yaml | 3 +- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 11 + drivers/clk/sophgo/Makefile | 7 + drivers/clk/sophgo/clk-cv1800.c | 1537 +++++++++++++++++ drivers/clk/sophgo/clk-cv1800.h | 123 ++ drivers/clk/sophgo/clk-cv18xx-common.c | 66 + drivers/clk/sophgo/clk-cv18xx-common.h | 81 + drivers/clk/sophgo/clk-cv18xx-ip.c | 887 ++++++++++ drivers/clk/sophgo/clk-cv18xx-ip.h | 261 +++ drivers/clk/sophgo/clk-cv18xx-pll.c | 420 +++++ drivers/clk/sophgo/clk-cv18xx-pll.h | 118 ++ 16 files changed, 3540 insertions(+), 6 deletions(-) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-cv1800.c create mode 100644 drivers/clk/sophgo/clk-cv1800.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h --- 2.44.0