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Wed, 27 Dec 2023 02:52:44 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::406a:664b:b8bc:1e6b]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::406a:664b:b8bc:1e6b%2]) with mapi id 15.20.7113.026; Wed, 27 Dec 2023 02:52:44 +0000 From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chao Wei , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 0/3] riscv: sophgo: add clock support for Sophgo CV1800 SoCs Date: Wed, 27 Dec 2023 10:52:02 +0800 Message-ID: X-Mailer: git-send-email 2.43.0 X-TMN: [QHCqluXM+ts8dfjtjqWldrizcAWJwGgl0OcNjwb0YDs=] X-ClientProxiedBy: TYAPR01CA0195.jpnprd01.prod.outlook.com (2603:1096:404:29::15) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231227025203.295571-1-inochiama@outlook.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|PH7PR20MB5948:EE_ X-MS-Office365-Filtering-Correlation-Id: d1a79c63-a1e8-4d88-2f0f-08dc0686e6b8 X-Microsoft-Antispam: BCL:0; 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This patch follow this patch series: https://lore.kernel.org/all/IA1PR20MB495399CAF2EEECC206ADA7ABBBD5A@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v4: 1. improve code for patch 2 2. remove the already applied bindings https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v3: 1. improve comment of patch 3 2. cleanup the include of patch 2 Changed from v2: 1. remove clock-names from bindings. 2. remove clock-frequency node of DT from previous patch. 3. change some unused clock to bypass mode to avoid unlockable PLL. Changed from v1: 1. fix license issues. Inochi Amaoto (3): clk: sophgo: Add CV1800 series clock controller driver riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 12 + drivers/clk/sophgo/Makefile | 7 + drivers/clk/sophgo/clk-cv1800.c | 1530 +++++++++++++++++++++++ drivers/clk/sophgo/clk-cv1800.h | 123 ++ drivers/clk/sophgo/clk-cv18xx-common.c | 66 + drivers/clk/sophgo/clk-cv18xx-common.h | 81 ++ drivers/clk/sophgo/clk-cv18xx-ip.c | 905 ++++++++++++++ drivers/clk/sophgo/clk-cv18xx-ip.h | 265 ++++ drivers/clk/sophgo/clk-cv18xx-pll.c | 425 +++++++ drivers/clk/sophgo/clk-cv18xx-pll.h | 119 ++ 15 files changed, 3560 insertions(+), 5 deletions(-) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-cv1800.c create mode 100644 drivers/clk/sophgo/clk-cv1800.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h --- 2.43.0