Message ID | cover.1701734442.git.unicorn_wang@outlook.com (mailing list archive) |
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Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e0THresJ" Received: from mail-oa1-x2d.google.com (mail-oa1-x2d.google.com [IPv6:2001:4860:4864:20::2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B42C8BB; Mon, 4 Dec 2023 16:22:19 -0800 (PST) Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1fb33059466so1216050fac.2; Mon, 04 Dec 2023 16:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701735739; x=1702340539; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=AceSiloMzdXvIE2DaEevBBcic/LsMH6cBLoMMH2zSsQ=; b=e0THresJi4EsBjzx1FHcR6oT2ZqDCFeIfUV3nRQudOkBac8hATihqgort2ubrZ9ZTo ziLUQc5MIJKr6qCZMo+1DIGY+nxQkQkd4oipuuEKuaM1CN9zf4nIegIOHlQaeBtyLmNt 1w70KkWfxrLqf4MO5OniUzagrdYqqZI++n1PtZ8Jo2Tzb5KhCNeNoYtPyR3Eh9j8Lsvs buG4A0WrqZ1oppiw3rh5gHJRYZPXseUSPkntJmhRHrOgayo+2sEL8l4EdS9FON+szYuu B13p8v1YYXGXmZMhv9s6TOSzebFonxj/Iyba5jBuNWFg+tZoGRO8aB4uytHEUPvvWWjj /xRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701735739; x=1702340539; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=AceSiloMzdXvIE2DaEevBBcic/LsMH6cBLoMMH2zSsQ=; b=oXCo2HmB1kKytA8cBhwShIMh50TNiT4uJzq8uohdtWOK6nVvf+h/gRdJsAwvryJu7U I4Zv30KCqKAr0pRzY9CCschYSEi6ZMnRZsIGxs0phVVMLGbzrFBPAn/7XqB9r62HCban sTs3mmoyHnsKIQQnxAYz+tm8nnU7ils5I62mKLsl33JRDA7uRpLnP1CYtO/9wENyoQXZ Of4imq7ab7l2AamqPOd8+zypkUxLnKKVGnp1z25P5ETb//QVishpuGjA4/A+VKSh8zLZ +4ygcF2nNF1h2dpZ/Fx5qUxCOM5eo2WwzO/b9rEwkJUkn5evPyjq3h42kSg1UmMqVb9A BK/A== X-Gm-Message-State: AOJu0YzwVeUHrll7kuhrop7lNJ5ISybkMItfCtHl8ptSQpZEFDgm73mK mqeZms7T+rzYB6x0m8872Xsng4HX6Zb9Yw== X-Google-Smtp-Source: AGHT+IGGpyH/uvDWZtUKbPGliRelSXQEiyxnYM/KxdFEwKMgIWFm+BsnmtfipMmVy4gfgRrC6v6CIg== X-Received: by 2002:a05:6871:4004:b0:1fa:26e7:c428 with SMTP id kx4-20020a056871400400b001fa26e7c428mr6236892oab.19.1701735738877; Mon, 04 Dec 2023 16:22:18 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id o11-20020a9d404b000000b006d87f95566bsm1142899oti.51.2023.12.04.16.22.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 16:22:18 -0800 (PST) From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang <unicorn_wang@outlook.com> Subject: [PATCH v4 0/4] riscv: sophgo: add clock support for sg2042 Date: Tue, 5 Dec 2023 08:22:06 +0800 Message-Id: <cover.1701734442.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: <linux-clk.vger.kernel.org> List-Subscribe: <mailto:linux-clk+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-clk+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
Series | riscv: sophgo: add clock support for sg2042 | expand |
From: Chen Wang <unicorn_wang@outlook.com> This series adds clock controller support for sophgo sg2042. Thanks, Chen --- Changes in v4: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5]. - dt-bindings: fixed a dt_binding_check error. Changes in v3: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3]. - DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4]. - Updating minor issues in dt-bindings as per input from reviews. Changes in v2: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2]. - Squashed the patch adding clock definitions with the patch adding the binding for the clock controller. - Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon. - DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC. - Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig. - Updated MAINTAINERS info. Changes in v1: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1]. Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v1 [1] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v2 [2] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v3 [3] Link: https://lore.kernel.org/linux-riscv/MA0P287MB03329AE180378E1A2E034374FE82A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/ [4] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v4 [5] --- Chen Wang (4): dt-bindings: soc: sophgo: Add Sophgo system control module dt-bindings: clock: sophgo: Add SG2042 bindings clk: sophgo: Add SG2042 clock generator driver riscv: dts: add clock generator for Sophgo SG2042 SoC .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 50 + .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 35 + MAINTAINERS | 7 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 79 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1371 +++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 226 +++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 169 ++ 12 files changed, 1953 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86