From patchwork Mon Jan 8 06:47:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13513035 Received: from mail-ot1-f47.google.com (mail-ot1-f47.google.com [209.85.210.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F9CC79EE; Mon, 8 Jan 2024 06:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aNk27Ju4" Received: by mail-ot1-f47.google.com with SMTP id 46e09a7af769-6dbd445f395so871695a34.2; Sun, 07 Jan 2024 22:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704696473; x=1705301273; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=eNqLWwBfGaYn9XJSIaItQtf1MNxpe69O24j9U8v8Pko=; b=aNk27Ju4Mn5gAaVeWJVVt0LrKEfOAMN1+50X7bn35lP6VkxbUcyXFD3jlSJs+UjDI8 r+2pZBfUVG/CJuqAxvsoCRXpv/rOVbwLOSV8TZYPx1Z/8kAKKrhHqZIQwrJzISFoH8vk vSQ+UeyofHEvkfMhEZQtdVMGomlBK3PmbjGhSobXKhAwdTCKmXnrZFcvRs7ke5traA1e iOchKD0eUBh7fDtlHP60eJmYjqvhSydIxpyRusRde3Jkz1ozhA0xarYx/LnWmcQlzGSO zPq4VYdxeZQN2mMg45E+NV49pIYGNca6C8IrWNQWZ5A/W+UZw/H4BHvt4Ghu3vEuLsGf FHbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704696473; x=1705301273; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=eNqLWwBfGaYn9XJSIaItQtf1MNxpe69O24j9U8v8Pko=; b=WA1CrjwKyj4iw+Xmq78Wi41GQuyc2X4z/KSY9O8kpmon/r0tFLG36W4vkx0Zq870kK nABqii+0EPQhxEb0da+ptEYbMnveRZrwEUQDEZHSK0royA0OkQ1N/u8TlzZ7Ch7w1loO 7yddVQrXDXoRWhpxtKBK+yzzzbUVvj3T/MNjhzkd+Usr7mHCabUoCcgMAPF+3f6tWOuE /ZnBiFLWaKqqafiHhYtaGD/NKsrSUyKhmvi3Wjxid95w6jiatIq/w+VZ6TTh0zhI9REI LY7yS45ZJacd3yvkPlUeKQ4dEyQT72MYNpJDOdE1fkqakwJ4Koz0yCBcEq87qS1HvbEe FW2Q== X-Gm-Message-State: AOJu0YxUwidydETEwx03EDhHwKSDFcutDro9meJyD7cdcXB/xpDuj1aN MQc08N1BCQW4uK3HhruiF7g= X-Google-Smtp-Source: AGHT+IEAed1LQOm4jnO2eZoQd48MGOblsDN0s+H3MVZ9h3pg6L7uNjJRnOkq3FBkJM9fob5C55G+ig== X-Received: by 2002:a9d:7308:0:b0:6dd:bf77:480 with SMTP id e8-20020a9d7308000000b006ddbf770480mr1453865otk.51.1704696472954; Sun, 07 Jan 2024 22:47:52 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id dw1-20020a05683033a100b006ddd602afccsm102718otb.66.2024.01.07.22.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jan 2024 22:47:52 -0800 (PST) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang Subject: [PATCH v7 0/4] riscv: sophgo: add clock support for sg2042 Date: Mon, 8 Jan 2024 14:47:41 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang This series adds clock controller support for sophgo sg2042. Thanks, Chen --- Changes in v7: The patch series is based on v6.7. You can simply review or test the patches at the link [8]. - fixed initval issue. - fixed pll clk crash issue. - fixed warning reported by - code optimization as per review comments. - code cleanup and style improvements as per review comments and checkpatch with "--strict" Changes in v6: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7]. - fixed some warnings/errors reported by kernel test robot . Changes in v5: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6]. - dt-bindings: improved yaml, such as: - add vendor prefix for system-ctrl property for clock generator. - Add explanation for system-ctrl property. - move sophgo,sg2042-clkgen.yaml to directly under clock folder. - fixed bugs for driver Makefile/Kconfig - continue cleaning-up debug print for driver code. Changes in v4: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5]. - dt-bindings: fixed a dt_binding_check error. Changes in v3: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3]. - DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4]. - Updating minor issues in dt-bindings as per input from reviews. Changes in v2: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2]. - Squashed the patch adding clock definitions with the patch adding the binding for the clock controller. - Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon. - DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC. - Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig. - Updated MAINTAINERS info. Changes in v1: The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1]. Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v1 [1] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v2 [2] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v3 [3] Link: https://lore.kernel.org/linux-riscv/MA0P287MB03329AE180378E1A2E034374FE82A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/ [4] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v4 [5] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v5 [6] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v6 [7] Link: https://github.com/unicornx/linux-riscv/commits/upstream-sg2042-clock-v7 [8] --- Chen Wang (4): dt-bindings: soc: sophgo: Add Sophgo system control module dt-bindings: clock: sophgo: support SG2042 clk: sophgo: Add SG2042 clock generator driver riscv: dts: add clock generator for Sophgo SG2042 SoC .../bindings/clock/sophgo,sg2042-clkgen.yaml | 53 + .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 34 + MAINTAINERS | 7 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 23 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1316 +++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 236 +++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 169 +++ 12 files changed, 1854 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h base-commit: 0dd3ee31125508cd67f7e7172247f05b7fd1753a