[v2,00/15] clk: renesas: rcar-gen4: Fractional PLL improvements

Message

Geert Uytterhoeven July 22, 2024, 11:50 a.m. UTC

Hi all,

Currently, almost all PLLs on R-Car Gen4 SoCs are modelled as fixed
divider clocks, based on the state of the mode pins.  The only exception
is PLL2 on R-Car V4H, which uses a custom clock driver to support High
Performance mode on the Cortex-A76 CPU cores.

However, the boot loader stack may have changed the actual PLL
configuration from the default, leading to incorrect clock frequencies.
A typical sympton is a CPU core running much slower than reported by
Linux.

This patch series enhances PLL support on R-Car Gen4 support by
obtaining the actual PLL configuration from the hardware.  As these PLLs
can be configured for fractional multiplication, an old patch to add
support fractional multiplication is revived, too.  Of course some
cleanups are included, too.

Changes compared to v1:
  - Add Reviewed-by,
  - Sort register definitions by register offset,
  - Use mul_u64_u32_shr() and div64_ul() helpers,
  - New patch "PATCH v2 15/15] clk: renesas: rcar-gen4: Remove unused
    default PLL2/3/4/6 configs".

I plan to queue this series in renesas-clk-for-v6.12.

Thanks for your comments!

Geert Uytterhoeven (15):
  clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions
  clk: renesas: rcar-gen4: Clarify custom PLL clock support
  clk: renesas: rcar-gen4: Use FIELD_GET()
  clk: renesas: rcar-gen4: Use defines for common CPG registers
  clk: renesas: rcar-gen4: Add support for fractional multiplication
  clk: renesas: rcar-gen4: Add support for variable fractional PLLs
  clk: renesas: rcar-gen4: Add support for fixed variable PLLs
  clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
  clk: renesas: r8a779a0: Use defines for PLL control registers
  clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
  clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
  clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
  clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
  clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
  clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs

 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  35 ++--
 drivers/clk/renesas/r8a779f0-cpg-mssr.c |  28 ++--
 drivers/clk/renesas/r8a779g0-cpg-mssr.c |  36 ++--
 drivers/clk/renesas/r8a779h0-cpg-mssr.c |  32 ++--
 drivers/clk/renesas/rcar-gen4-cpg.c     | 210 ++++++++++++++++--------
 drivers/clk/renesas/rcar-gen4-cpg.h     |  36 ++--
 6 files changed, 230 insertions(+), 147 deletions(-)