Show patches with: Submitter = Michael Tretter       |   55 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2] clk: zynqmp: replace warn_once with pr_debug for failed clock ops [v2] clk: zynqmp: replace warn_once with pr_debug for failed clock ops 1 - - --- 2022-01-19 Michael Tretter Accepted
clk: zynqmp: warn always when a clock op fails clk: zynqmp: warn always when a clock op fails - - - --- 2022-01-12 Michael Tretter Changes Requested
clk: xilinx: vcu: rewrite and fix xvcu_clk_hw_unregister_leaf clk: xilinx: vcu: rewrite and fix xvcu_clk_hw_unregister_leaf - - - --- 2021-03-18 Michael Tretter Not Applicable
[v3,15/15] clk: xilinx: move xlnx_vcu clock driver from soc soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,14/15] soc: xilinx: vcu: fix alignment to open parenthesis soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,13/15] soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,12/15] soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: Convert driver to clock provider 1 1 - --- 2021-01-21 Michael Tretter Accepted
[v3,11/15] soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,10/15] soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,09/15] soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,08/15] soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,07/15] soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,06/15] soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,05/15] soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,04/15] soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu soc: xilinx: vcu: Convert driver to clock provider 1 - - --- 2021-01-21 Michael Tretter Accepted
[v3,02/15] clk: divider: fix initialization with parent_hw soc: xilinx: vcu: Convert driver to clock provider 1 1 - --- 2021-01-21 Michael Tretter Accepted
[v3,01/15] ARM: dts: vcu: define indexes for output clocks soc: xilinx: vcu: Convert driver to clock provider 3 - - --- 2021-01-21 Michael Tretter Accepted
[v2,15/15] clk: xilinx: move xlnx_vcu clock driver from soc soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,14/15] soc: xilinx: vcu: fix alignment to open parenthesis soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,13/15] soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,12/15] soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: Convert driver to clock provider - 1 - --- 2020-12-21 Michael Tretter Superseded
[v2,11/15] soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,10/15] soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,09/15] soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,08/15] soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,07/15] soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,06/15] soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,05/15] soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,04/15] soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu soc: xilinx: vcu: Convert driver to clock provider - - - --- 2020-12-21 Michael Tretter Superseded
[v2,02/15] clk: divider: fix initialization with parent_hw soc: xilinx: vcu: Convert driver to clock provider - 1 - --- 2020-12-21 Michael Tretter Superseded
[v2,01/15] ARM: dts: vcu: define indexes for output clocks soc: xilinx: vcu: Convert driver to clock provider 2 - - --- 2020-12-21 Michael Tretter Superseded
[12/12] soc: xilinx: vcu: use bitfields for register definition [01/12] ARM: dts: define indexes for output clocks - 1 - --- 2020-11-16 Michael Tretter Not Applicable
[11/12] soc: xilinx: vcu: remove calculation of PLL configuration [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[10/12] soc: xilinx: vcu: make the PLL configurable [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[09/12] soc: xilinx: vcu: make pll post divider explicit [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[08/12] soc: xilinx: vcu: implement clock provider for output clocks [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Changes Requested
[07/12] soc: xilinx: vcu: register PLL as fixed rate clock [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[06/12] soc: xilinx: vcu: implement PLL disable [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[05/12] soc: xilinx: vcu: add helpers for configuring PLL [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[04/12] soc: xilinx: vcu: add helper to wait for PLL locked [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu [01/12] ARM: dts: define indexes for output clocks - - - --- 2020-11-16 Michael Tretter Not Applicable
[02/12] clk: divider: fix initialization with parent_hw [01/12] ARM: dts: define indexes for output clocks - 1 - --- 2020-11-16 Michael Tretter Awaiting Upstream
[01/12] ARM: dts: define indexes for output clocks [01/12] ARM: dts: define indexes for output clocks 2 - - --- 2020-11-16 Michael Tretter Awaiting Upstream
[v3] clk: zynqmp: use structs for clk query responses [v3] clk: zynqmp: use structs for clk query responses - 1 - --- 2019-04-12 Michael Tretter Accepted
[v2,4/4] clk: zynqmp: use structs for clk query responses clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-19 Michael Tretter Changes Requested
[v2,3/4] clk: zynqmp: fix check for fractional clock clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-19 Michael Tretter Accepted
[v2,2/4] clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-19 Michael Tretter Accepted
[v2,1/4] clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-19 Michael Tretter Accepted
[5/5] clk: zynqmp: make field definitions of query responses consistent clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-12 Michael Tretter Changes Requested
[4/5] clk: zynqmp: cleanup sizes of firmware responses clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-12 Michael Tretter Changes Requested
[3/5] clk: zynqmp: do not export zynqmp_clk_register_mux clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-12 Michael Tretter Changes Requested
[2/5] clk: zynqmp: fix doc of __zynqmp_clock_get_parents clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-12 Michael Tretter Awaiting Upstream
[1/5] clk: zynqmp: fix check for fractional clock clk: zynqmp: fix CLK_FRAC and various cleanups - - - --- 2019-03-12 Michael Tretter Changes Requested