Show patches with: Submitter = Aapo Vienamo       |   22 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks 2 - - --- 2018-07-12 Aapo Vienamo Accepted
[v6,3/4] clk: tegra: Add sdmmc mux divider clock 2 - - --- 2018-07-12 Aapo Vienamo Accepted
[v6,2/4] clk: tegra: Refactor fractional divider calculation 2 - - --- 2018-07-12 Aapo Vienamo Accepted
[v6,1/4] clk: tegra: Fix includes required by fence_udelay() 2 - - --- 2018-07-12 Aapo Vienamo Accepted
[v5,4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks 1 - - --- 2018-07-11 Aapo Vienamo Superseded
[v5,3/4] clk: tegra: Add sdmmc mux divider clock 1 - - --- 2018-07-11 Aapo Vienamo Changes Requested
[v5,2/4] clk: tegra: refactor 7.1 div calculation 2 - - --- 2018-07-11 Aapo Vienamo Superseded
[v5,1/4] clk: tegra: Fix includes required by fence_udelay() 2 - - --- 2018-07-11 Aapo Vienamo Superseded
[v4,4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v4,3/4] clk: tegra: Add sdmmc mux divider clock 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v4,2/4] clk: tegra: refactor 7.1 div calculation 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v4,1/4] clk: tegra: Fix includes required by fence_udelay() - - - --- 2018-07-09 Aapo Vienamo Superseded
[v3,4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v3,3/4] clk: tegra: Add sdmmc mux divider clock 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v3,2/4] clk: tegra: refactor 7.1 div calculation 1 - - --- 2018-07-09 Aapo Vienamo Superseded
[v3,1/4] clk: tegra: Fix includes required by fence_udelay() - - - --- 2018-07-09 Aapo Vienamo Superseded
[v2,3/3] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks - - - --- 2018-07-04 Aapo Vienamo Changes Requested
[v2,2/3] clk: tegra: Add sdmmc mux divider clock - - - --- 2018-07-04 Aapo Vienamo Changes Requested
[v2,1/3] clk: tegra: refactor 7.1 div calculation - - - --- 2018-07-04 Aapo Vienamo Changes Requested
[3/3] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks - - - --- 2018-07-03 Aapo Vienamo Changes Requested
[2/3] clk: tegra: Add sdmmc mux divider clock - - - --- 2018-07-03 Aapo Vienamo Changes Requested
[1/3] clk: tegra: refactor 7.1 div calculation - - - --- 2018-07-03 Aapo Vienamo Changes Requested