Show patches with: Submitter = Martin Blumenstingl       |   220 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,4/4] clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: switch from .round_rate to .determine_rate - - - --- 2022-12-25 Martin Blumenstingl Awaiting Upstream
[v1,3/4] clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: switch from .round_rate to .determine_rate - - - --- 2022-12-25 Martin Blumenstingl Awaiting Upstream
[v1,2/4] clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: switch from .round_rate to .determine_rate - - - --- 2022-12-25 Martin Blumenstingl Awaiting Upstream
[v1,1/4] clk: meson: mpll: Switch from .round_rate to .determine_rate clk: meson: switch from .round_rate to .determine_rate - - - --- 2022-12-25 Martin Blumenstingl Awaiting Upstream
[v3] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB [v3] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB - - 1 --- 2021-10-31 Martin Blumenstingl Awaiting Upstream
[v2] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB [v2] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB - - 1 --- 2021-10-27 Martin Blumenstingl Superseded
clk: meson: gxbb: Add the spread spectrum bit for MPLL0 on GXBB clk: meson: gxbb: Add the spread spectrum bit for MPLL0 on GXBB - - 1 --- 2021-10-16 Martin Blumenstingl Changes Requested
[clk-fixes,v1,2/2] clk: composite: Use rate_ops.determine_rate when also a mux is available Fix clk-composite to support .determine_rate - - - --- 2021-10-16 Martin Blumenstingl Accepted
[clk-fixes,v1,1/2] clk: composite: Also consider .determine_rate for rate + mux composites Fix clk-composite to support .determine_rate - - - --- 2021-10-16 Martin Blumenstingl Accepted
clk: composite: Also consider .determine_rate for rate + mux composites clk: composite: Also consider .determine_rate for rate + mux composites - - - --- 2021-10-15 Martin Blumenstingl Changes Requested
[6/6] clk: meson: meson8b: Export the video clocks clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[5/6] clk: meson: meson8b: Make the video clock trees mutable clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[4/6] clk: meson: meson8b: Initialize the HDMI PLL registers clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[3/6] clk: meson: meson8b: Add the HDMI PLL M/N parameters clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[2/6] clk: meson: meson8b: Add the vid_pll_lvds_en gate clock clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[1/6] clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel clk: meson8b: video clock tree fixes and making it mutable - - - --- 2021-07-13 Martin Blumenstingl Awaiting Upstream
[v1,6/6] clk: stm32mp1: Switch to clk_divider.determine_rate clk: switch dividers to .determine_rate - - - --- 2021-07-02 Martin Blumenstingl Accepted
[v1,5/6] clk: stm32h7: Switch to clk_divider.determine_rate clk: switch dividers to .determine_rate - - - --- 2021-07-02 Martin Blumenstingl Accepted
[v1,4/6] clk: stm32f4: Switch to clk_divider.determine_rate clk: switch dividers to .determine_rate - - - --- 2021-07-02 Martin Blumenstingl Accepted
[v1,3/6] clk: bcm2835: Switch to clk_divider.determine_rate clk: switch dividers to .determine_rate - - 1 --- 2021-07-02 Martin Blumenstingl Accepted
[v1,2/6] clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate clk: switch dividers to .determine_rate - 1 - --- 2021-07-02 Martin Blumenstingl Awaiting Upstream
[v1,1/6] clk: divider: Implement and wire up .determine_rate by default clk: switch dividers to .determine_rate - - - --- 2021-07-02 Martin Blumenstingl Accepted
[v3,3/3] clk: meson: regmap: switch to determine_rate for the dividers clk: meson: rounding for fast clocks on 32-bit SoCs - 1 - --- 2021-06-27 Martin Blumenstingl Accepted
[v3,2/3] clk: divider: Switch from .round_rate to .determine_rate by default clk: meson: rounding for fast clocks on 32-bit SoCs - 1 - --- 2021-06-27 Martin Blumenstingl Accepted
[v3,1/3] clk: divider: Add re-usable determine_rate implementations clk: meson: rounding for fast clocks on 32-bit SoCs - 1 - --- 2021-06-27 Martin Blumenstingl Accepted
[v2] clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel [v2] clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel - - - --- 2021-05-24 Martin Blumenstingl Changes Requested
clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel - - - --- 2021-05-24 Martin Blumenstingl Changes Requested
[v2,3/3] clk: meson: regmap: switch to determine_rate for the dividers clk: meson: rounding for fast clocks on 32-bit SoCs - 1 - --- 2021-05-24 Martin Blumenstingl Superseded
[v2,2/3] clk: divider: Switch from .round_rate to .determine_rate by default clk: meson: rounding for fast clocks on 32-bit SoCs - - - --- 2021-05-24 Martin Blumenstingl Superseded
[v2,1/3] clk: divider: Add re-usable determine_rate implementations clk: meson: rounding for fast clocks on 32-bit SoCs - - - --- 2021-05-24 Martin Blumenstingl Superseded
[RFC,v1,3/3] clk: meson: pll: switch to determine_rate for the PLL ops clk: meson: rounding for fast clocks on 32-bit SoCs - - - --- 2021-05-17 Martin Blumenstingl Superseded
[RFC,v1,2/3] clk: meson: regmap: switch to determine_rate for the dividers clk: meson: rounding for fast clocks on 32-bit SoCs - 1 - --- 2021-05-17 Martin Blumenstingl Superseded
[RFC,v1,1/3] clk: divider: Add re-usable determine_rate implementations clk: meson: rounding for fast clocks on 32-bit SoCs - - - --- 2021-05-17 Martin Blumenstingl Superseded
[5/5] clk: meson: meson8b: add the vid_pll_lvds_en gate clock clk: meson8b: video clock tree updates - - - --- 2021-01-04 Martin Blumenstingl Awaiting Upstream
[4/5] clk: meson: meson8b: add the HDMI PLL M/N parameters clk: meson8b: video clock tree updates - - - --- 2021-01-04 Martin Blumenstingl Awaiting Upstream
[3/5] clk: meson: meson8b: add the video clock divider tables clk: meson8b: video clock tree updates - - - --- 2021-01-04 Martin Blumenstingl Awaiting Upstream
[2/5] clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock clk: meson8b: video clock tree updates - - - --- 2021-01-04 Martin Blumenstingl Awaiting Upstream
[1/5] clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel clk: meson8b: video clock tree updates - - - --- 2021-01-04 Martin Blumenstingl Awaiting Upstream
[3/3] clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: three small clk-pll fixes - - - --- 2020-12-26 Martin Blumenstingl Awaiting Upstream
[2/3] clk: meson: clk-pll: make "ret" a signed integer clk: meson: three small clk-pll fixes - - - --- 2020-12-26 Martin Blumenstingl Awaiting Upstream
[1/3] clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL clk: meson: three small clk-pll fixes - - - --- 2020-12-26 Martin Blumenstingl Awaiting Upstream
[2/2] dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson8b: cleanup unused code - - - --- 2020-12-21 Martin Blumenstingl Awaiting Upstream
[1/2] clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson8b: cleanup unused code - - - --- 2020-12-21 Martin Blumenstingl Awaiting Upstream
[2/2] clk: meson: meson8b: add the vclk2_en gate clock clk: meson8b: add two missing gate clocks - - - --- 2020-06-29 Martin Blumenstingl Awaiting Upstream
[1/2] clk: meson: meson8b: add the vclk_en gate clock clk: meson8b: add two missing gate clocks - - - --- 2020-06-29 Martin Blumenstingl Awaiting Upstream
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 - 1 - --- 2020-06-20 Martin Blumenstingl Awaiting Upstream
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers - - - --- 2020-05-01 Martin Blumenstingl Awaiting Upstream
[v2,4/4] clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson8b: updates for video clocks / resets - - - --- 2020-04-17 Martin Blumenstingl Awaiting Upstream
[v2,3/4] clk: meson: meson8b: Fix the vclk_div{1,2,4,6,12}_en gate bits clk: meson8b: updates for video clocks / resets - - - --- 2020-04-17 Martin Blumenstingl Awaiting Upstream
[v2,2/4] clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson8b: updates for video clocks / resets - - - --- 2020-04-17 Martin Blumenstingl Awaiting Upstream
[v2,1/4] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson8b: updates for video clocks / resets - - - --- 2020-04-17 Martin Blumenstingl Awaiting Upstream
[4/4] clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson8b: updates for video clocks / resets - - - --- 2020-04-14 Martin Blumenstingl Superseded
[3/4] clk: meson: meson8b: Fix the vclk_div{1,2,4,6,12}_en gate bits clk: meson8b: updates for video clocks / resets - - - --- 2020-04-14 Martin Blumenstingl Superseded
[2/4] clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson8b: updates for video clocks / resets - - - --- 2020-04-14 Martin Blumenstingl Superseded
[1/4] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson8b: updates for video clocks / resets - - - --- 2020-04-14 Martin Blumenstingl Superseded
[v2,2/2] clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: prepare GX and G12 for GPU DVFS - - - --- 2020-04-14 Martin Blumenstingl Awaiting Upstream
[v2,1/2] clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: prepare GX and G12 for GPU DVFS - - - --- 2020-04-14 Martin Blumenstingl Awaiting Upstream
[2/2] clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: allow the HDMI driver to manage "hdmi_sys" - - - --- 2020-03-30 Martin Blumenstingl Awaiting Upstream
[1/2] clk: meson8b: export the HDMI system clock clk: meson8b: allow the HDMI driver to manage "hdmi_sys" 1 - - --- 2020-03-30 Martin Blumenstingl Awaiting Upstream
[RFC,v1,5/5] arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 - - - --- 2020-03-30 Martin Blumenstingl RFC
[RFC,v1,4/5] arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 - - - --- 2020-03-30 Martin Blumenstingl RFC
[RFC,v1,3/5] arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 - - - --- 2020-03-30 Martin Blumenstingl RFC
[RFC,v1,2/5] clk: meson: g12a: Prepare the GPU clock tree to change at runtime GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 - - - --- 2020-03-30 Martin Blumenstingl RFC
[RFC,v1,1/5] clk: meson: gxbb: Prepare the GPU clock tree to change at runtime GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 - - - --- 2020-03-30 Martin Blumenstingl RFC
clk: meson: meson8b: set audio output clock hierarchy clk: meson: meson8b: set audio output clock hierarchy - 1 - --- 2020-02-20 Martin Blumenstingl Awaiting Upstream
[v2,2/2] clk: clarify that clk_set_rate() does updates from top to bottom clk: Meson8/8b/8m2: fix the mali clock flags 1 - - --- 2019-12-26 Martin Blumenstingl Awaiting Upstream
[v2,1/2] clk: meson: meson8b: make the CCF use the glitch-free "mali" mux clk: Meson8/8b/8m2: fix the mali clock flags - - - --- 2019-12-26 Martin Blumenstingl Awaiting Upstream
[1/1] clk: meson: meson8b: make the CCF use the glitch-free "mali" mux clk: Meson8/8b/8m2: fix the mali clock flags - - - --- 2019-12-15 Martin Blumenstingl Awaiting Upstream
[v3,2/2] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,1/2] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding add the DDR clock controller on Meson8 and Meson8b 1 1 - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,5/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,3/5] clk: meson: meson8b: change references to the XTAL clock to use [fw_]name provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v3,1/5] dt-bindings: clock: meson8b: add the clock inputs provide the XTAL clock via OF on Meson8/8b/8m2 - 1 - --- 2019-11-17 Martin Blumenstingl Awaiting Upstream
[v2,5/5] ARM: dts: meson8b: add the DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-10-27 Martin Blumenstingl Not Applicable
[v2,4/5] ARM: dts: meson8: add the DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-10-27 Martin Blumenstingl Not Applicable
[v2,3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks add the DDR clock controller on Meson8 and Meson8b 1 - - --- 2019-10-27 Martin Blumenstingl Awaiting Upstream
[v2,2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-10-27 Martin Blumenstingl Changes Requested
[v2,1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding add the DDR clock controller on Meson8 and Meson8b 1 1 - --- 2019-10-27 Martin Blumenstingl Awaiting Upstream
[v2,5/5] ARM: dts: meson: provide the XTAL clock using a fixed-clock provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-10-27 Martin Blumenstingl Not Applicable
[v2,4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-10-27 Martin Blumenstingl Awaiting Upstream
[v2,3/5] clk: meson: meson8b: change references to the XTAL clock to use the name provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-10-27 Martin Blumenstingl Changes Requested
[v2,2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-10-27 Martin Blumenstingl Awaiting Upstream
[v2,1/5] dt-bindings: clock: meson8b: add the clock inputs provide the XTAL clock via OF on Meson8/8b/8m2 - 1 - --- 2019-10-27 Martin Blumenstingl Awaiting Upstream
[6/6] ARM: dts: meson8b: add the DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-09-21 Martin Blumenstingl Not Applicable
[5/6] ARM: dts: meson8: add the DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-09-21 Martin Blumenstingl Not Applicable
[4/6] clk: meson: meson8b: add the ddr_pll input for the audio clocks add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-09-21 Martin Blumenstingl Changes Requested
[3/6] clk: meson: meson8b: use of_clk_hw_register to register the clocks add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller add the DDR clock controller on Meson8 and Meson8b - - - --- 2019-09-21 Martin Blumenstingl Changes Requested
[1/6] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding add the DDR clock controller on Meson8 and Meson8b - 1 - --- 2019-09-21 Martin Blumenstingl Changes Requested
[5/5] ARM: dts: meson: provide the XTAL clock using a fixed-clock provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-09-21 Martin Blumenstingl Not Applicable
[4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[3/5] clk: meson: meson8b: change references to the XTAL clock to use the name provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier provide the XTAL clock via OF on Meson8/8b/8m2 - - - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[1/5] dt-bindings: clock: meson8b: add the clock inputs provide the XTAL clock via OF on Meson8/8b/8m2 - 1 - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate [1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate - - - --- 2019-09-21 Martin Blumenstingl Awaiting Upstream
[RFC,v1] clk: Fix potential NULL dereference in clk_fetch_parent_index() [RFC,v1] clk: Fix potential NULL dereference in clk_fetch_parent_index() - - - --- 2019-08-15 Martin Blumenstingl Accepted
[1/1] clk: pwm: implement the .get_duty_cycle callback clk-pwm: show duty cycle in debugfs - - - --- 2019-05-25 Martin Blumenstingl Accepted
[4/4] clk: meson: meson8b: add the cts_i958 clock 32-bit Meson: audio clock support - - - --- 2019-05-20 Martin Blumenstingl Awaiting Upstream
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