Show patches with: Submitter = Guodong Xu       |   11 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
clk: hi3660: fix incorrect uart3 clock freqency - - - --- 2017-08-07 Guodong Xu Accepted
[v2,3/3] clk: hi3660: Set PPLL2 to 2880M 1 - - --- 2017-05-26 Guodong Xu sboyd Accepted
[v2,2/3] clk: hi3660: add clocks for video encoder, decoder and ISP 1 1 - --- 2017-05-26 Guodong Xu sboyd Accepted
[v2,1/3] clk: hi3660: fix wrong parent name of clk_mux_sysbus 1 - - --- 2017-05-26 Guodong Xu sboyd Accepted
[3/3] clk: hi3660: Set PPLL2 to 2880M - - - --- 2017-05-15 Guodong Xu Superseded
[2/3] clk: hi3660: add clocks for video encoder and decoder - - - --- 2017-05-15 Guodong Xu Superseded
[1/3] clk: hi3660: fix wrong parent name of clk_mux_sysbus - - - --- 2017-05-15 Guodong Xu Superseded
[v2,2/2] clk: hi6220: initialize UART1 clock to 150MHz - - - --- 2016-06-29 Guodong Xu mturquette Superseded
[v2,1/2] clk: hi6220: Change syspll and media_syspll clk to 1.19GHz - - - --- 2016-06-29 Guodong Xu mturquette Accepted
[2/2] clk: hi6220: initialize UART1 clock to 150MHz - - - --- 2016-06-28 Guodong Xu Superseded
[1/2] clk: hi6220: Change syspll and media_syspll clk to 1.19GHz - - - --- 2016-06-28 Guodong Xu Superseded