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Patch Series A/R/T S/W/F Date Submitter Delegate State
[-next] clk: mediatek: fix platform_no_drv_owner.cocci warnings [-next] clk: mediatek: fix platform_no_drv_owner.cocci warnings - - - --- 2020-09-22 Zou Wei Accepted
[-next] clk: imx: gate2: Remove unused variable ret [-next] clk: imx: gate2: Remove unused variable ret - 1 - --- 2020-11-03 Zou Wei Awaiting Upstream
[-next] clk: imx: scu: Make pd_np with static keyword [-next] clk: imx: scu: Make pd_np with static keyword - 1 - --- 2020-11-04 Zou Wei Awaiting Upstream
[RFC,2/4] clk: mdm9615: Add EBI2 clock - - - --- 2016-12-22 Zoran Markovic sboyd Changes Requested
[RFC,PATCHv2,2/4] clk: mdm9615: Add EBI2 clock 1 - - --- 2016-12-23 Zoran Markovic sboyd Accepted
[1/4] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 - - - --- 2020-10-16 Zong Li Changes Requested
[2/4] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 1 - --- 2020-10-16 Zong Li Awaiting Upstream
[3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 - - - --- 2020-10-16 Zong Li Awaiting Upstream
[4/4] clk: sifive: Refactor __prci_clock array by using macro clk: add driver for the SiFive FU740 - - - --- 2020-10-16 Zong Li Changes Requested
[v2,1/3] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 - - - --- 2020-11-10 Zong Li Superseded
[v2,2/3] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 2 - --- 2020-11-10 Zong Li Superseded
[v2,3/3] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 - - - --- 2020-11-10 Zong Li Changes Requested
[v3,1/3] clk: sifive: Extract prci core to common base [v3,1/3] clk: sifive: Extract prci core to common base - 1 - --- 2020-11-11 Zong Li Superseded
[v3,2/3] clk: sifive: Use common name for prci configuration [v3,1/3] clk: sifive: Extract prci core to common base 1 2 - --- 2020-11-11 Zong Li Superseded
[v3,3/3] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block [v3,1/3] clk: sifive: Extract prci core to common base - 1 - --- 2020-11-11 Zong Li Superseded
[v4,1/4] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 1 1 - --- 2020-11-11 Zong Li Superseded
[v4,2/4] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 2 - --- 2020-11-11 Zong Li Superseded
[v4,3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 1 1 - --- 2020-11-11 Zong Li Superseded
[v4,4/4] clk: sifive: Fix the wrong bit field shift clk: add driver for the SiFive FU740 - - - --- 2020-11-11 Zong Li Superseded
[v5,1/5] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 1 1 - --- 2020-11-30 Zong Li Superseded
[v5,2/5] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 2 - --- 2020-11-30 Zong Li Superseded
[v5,3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 1 1 - --- 2020-11-30 Zong Li Superseded
[v5,4/5] clk: sifive: Fix the wrong bit field shift clk: add driver for the SiFive FU740 - - - --- 2020-11-30 Zong Li Superseded
[v5,5/5] clk: sifive: Add clock enable and disable ops clk: add driver for the SiFive FU740 - - - --- 2020-11-30 Zong Li Superseded
[v6,1/5] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 1 1 - --- 2020-12-08 Zong Li Changes Requested
[v6,2/5] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 2 - --- 2020-12-08 Zong Li Superseded
[v6,3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 1 1 - --- 2020-12-08 Zong Li Superseded
[v6,4/5] clk: sifive: Fix the wrong bit field shift clk: add driver for the SiFive FU740 - - - --- 2020-12-08 Zong Li Superseded
[v6,5/5] clk: sifive: Add clock enable and disable ops clk: add driver for the SiFive FU740 - - 1 --- 2020-12-08 Zong Li Superseded
[v7,1/5] clk: sifive: Extract prci core to common base clk: add driver for the SiFive FU740 1 1 - --- 2020-12-09 Zong Li Accepted
[v7,2/5] clk: sifive: Use common name for prci configuration clk: add driver for the SiFive FU740 1 2 - --- 2020-12-09 Zong Li Accepted
[v7,3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: add driver for the SiFive FU740 1 1 - --- 2020-12-09 Zong Li Accepted
[v7,4/5] clk: sifive: Fix the wrong bit field shift clk: add driver for the SiFive FU740 - - - --- 2020-12-09 Zong Li Accepted
[v7,5/5] clk: sifive: Add clock enable and disable ops clk: add driver for the SiFive FU740 - - 1 --- 2020-12-09 Zong Li Accepted
[1/1] clk: sifive: Fix W=1 kernel build warning [1/1] clk: sifive: Fix W=1 kernel build warning - - - --- 2021-12-08 Zong Li Changes Requested
[v2,1/1] clk: sifive: Fix W=1 kernel build warning [v2,1/1] clk: sifive: Fix W=1 kernel build warning - - - --- 2021-12-08 Zong Li Changes Requested
[v3] clk: sifive: Fix W=1 kernel build warning [v3] clk: sifive: Fix W=1 kernel build warning - - - --- 2022-01-06 Zong Li Changes Requested
[v3,RESEND] clk: sifive: Fix W=1 kernel build warning [v3,RESEND] clk: sifive: Fix W=1 kernel build warning - - - --- 2022-01-07 Zong Li Changes Requested
[v4] clk: sifive: Fix W=1 kernel build warning [v4] clk: sifive: Fix W=1 kernel build warning - - - --- 2022-01-10 Zong Li Changes Requested
clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT - 1 - --- 2022-01-11 Zixun LI Under Review
[1/2] dt-bindings: clock: Add X1000 bindings. [1/2] dt-bindings: clock: Add X1000 bindings. - - - --- 2019-10-18 Zhou Yanjie Superseded
[2/2] clk: Ingenic: Add CGU driver for X1000. [1/2] dt-bindings: clock: Add X1000 bindings. - - - --- 2019-10-18 Zhou Yanjie Changes Requested
[1/2,v2] dt-bindings: clock: Add X1000 bindings. [1/2,v2] dt-bindings: clock: Add X1000 bindings. - 1 - --- 2019-10-22 Zhou Yanjie Superseded
[2/2,v2] clk: Ingenic: Add CGU driver for X1000. [1/2,v2] dt-bindings: clock: Add X1000 bindings. 1 - - --- 2019-10-22 Zhou Yanjie Superseded
[1/2,v3] dt-bindings: clock: Add X1000 bindings. [1/2,v3] dt-bindings: clock: Add X1000 bindings. - 1 - --- 2019-11-10 Zhou Yanjie Accepted
[2/2,v3] clk: Ingenic: Add CGU driver for X1000. [1/2,v3] dt-bindings: clock: Add X1000 bindings. - 1 - --- 2019-11-10 Zhou Yanjie Accepted
[1/5] clk: Ingenic: Adjust code to make it compatible with X1830. [1/5] clk: Ingenic: Adjust code to make it compatible with X1830. - - - --- 2019-11-27 Zhou Yanjie Changes Requested
[2/5] dt-bindings: clock: Add X1830 bindings. [1/5] clk: Ingenic: Adjust code to make it compatible with X1830. - 1 - --- 2019-11-27 Zhou Yanjie Superseded
[3/5] clk: Ingenic: Add CGU driver for X1830. [1/5] clk: Ingenic: Adjust code to make it compatible with X1830. - - - --- 2019-11-27 Zhou Yanjie Superseded
[4/5] dt-bindings: clock: Add USB OTG clock for X1000. [1/5] clk: Ingenic: Adjust code to make it compatible with X1830. - - - --- 2019-11-27 Zhou Yanjie Changes Requested
[5/5] clk: Ingenic: Add USB OTG clock for X1000. [1/5] clk: Ingenic: Adjust code to make it compatible with X1830. - - - --- 2019-11-27 Zhou Yanjie Superseded
[v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. [v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. - - - --- 2019-12-13 Zhou Yanjie Changes Requested
[v2,2/5] clk: Ingenic: Adjust code to make it compatible with new cgu code. [v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. - - - --- 2019-12-13 Zhou Yanjie Superseded
[v2,3/5] dt-bindings: clock: Add X1830 bindings. [v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. - 1 - --- 2019-12-13 Zhou Yanjie Superseded
[v2,4/5] clk: Ingenic: Add CGU driver for X1830. [v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. - - - --- 2019-12-13 Zhou Yanjie Superseded
[v2,5/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. [v2,1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. - - - --- 2019-12-13 Zhou Yanjie Superseded
[v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. [v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-14 Zhou Yanjie Changes Requested
[v3,2/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830. [v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-14 Zhou Yanjie Changes Requested
[v3,3/5] clk: Ingenic: Adjust code to make it compatible with new cgu code. [v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-14 Zhou Yanjie Superseded
[v3,4/5] dt-bindings: clock: Add X1830 bindings. [v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. - 1 - --- 2019-12-14 Zhou Yanjie Superseded
[v3,5/5] clk: Ingenic: Add CGU driver for X1830. [v3,1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-14 Zhou Yanjie Superseded
[v4,1/4] clk: Ingenic: Remove unnecessary spinlock when reading registers. [v4,1/4] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-15 Zhou Yanjie Superseded
[v4,2/4] clk: Ingenic: Adjust cgu code to make it compatible with X1830. [v4,1/4] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-15 Zhou Yanjie Superseded
[v4,3/4] dt-bindings: clock: Add X1830 bindings. [v4,1/4] clk: Ingenic: Remove unnecessary spinlock when reading registers. - 1 - --- 2019-12-15 Zhou Yanjie Superseded
[v4,4/4] clk: Ingenic: Add CGU driver for X1830. [v4,1/4] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2019-12-15 Zhou Yanjie Superseded
[v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-02-14 Zhou Yanjie Awaiting Upstream
[v5,2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-02-14 Zhou Yanjie Changes Requested
[v5,3/6] dt-bindings: clock: Add X1830 bindings. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - 1 - --- 2020-02-14 Zhou Yanjie Awaiting Upstream
[v5,4/6] clk: Ingenic: Add CGU driver for X1830. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-02-14 Zhou Yanjie Awaiting Upstream
[v5,5/6] dt-bindings: clock: Add and reorder ABI for X1000. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. 1 - - --- 2020-02-14 Zhou Yanjie Awaiting Upstream
[v5,6/6] clk: X1000: Add FIXDIV for SSI clock of X1000. [v5,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-02-14 Zhou Yanjie Awaiting Upstream
[v4,1/6] MIPS: JZ4780: Introduce SMP support. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Changes Requested
[v4,2/6] clocksource: Ingenic: Add high resolution timer support for SMP. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Not Applicable
[v4,3/6] dt-bindings: MIPS: Document Ingenic SoCs binding. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Not Applicable
[v4,4/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Not Applicable
[v4,5/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Not Applicable
[v4,6/6] MIPS: CI20: Update defconfig to support SMP. [v4,1/6] MIPS: JZ4780: Introduce SMP support. - - 2 --- 2020-02-14 Zhou Yanjie Not Applicable
[v5,1/7] clk: JZ4780: Add function for enable the second core. [v5,1/7] clk: JZ4780: Add function for enable the second core. - 1 2 --- 2020-02-15 Zhou Yanjie Changes Requested
[v5,2/7] MIPS: JZ4780: Introduce SMP support. [v5,1/7] clk: JZ4780: Add function for enable the second core. - 1 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[v5,3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP. [v5,1/7] clk: JZ4780: Add function for enable the second core. - - 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[v5,4/7] clocksource: Ingenic: Add high resolution timer support for SMP. [v5,1/7] clk: JZ4780: Add function for enable the second core. - - 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[v5,5/7] dt-bindings: MIPS: Document Ingenic SoCs binding. [v5,1/7] clk: JZ4780: Add function for enable the second core. - - 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[v5,6/7] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs. [v5,1/7] clk: JZ4780: Add function for enable the second core. - - 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[v5,7/7] MIPS: CI20: Update defconfig to support SMP. [v5,1/7] clk: JZ4780: Add function for enable the second core. - - 2 --- 2020-02-15 Zhou Yanjie Not Applicable
[1/4] dt-bindings: timer: Add X1000 bindings. [1/4] dt-bindings: timer: Add X1000 bindings. 1 - - --- 2020-02-19 Zhou Yanjie Not Applicable
[2/4] clk: Ingenic: Add support for TCU of X1000. [1/4] dt-bindings: timer: Add X1000 bindings. 1 - - --- 2020-02-19 Zhou Yanjie Awaiting Upstream
[3/4] clocksource: Ingenic: Add support for TCU of X1000. [1/4] dt-bindings: timer: Add X1000 bindings. - - - --- 2020-02-19 Zhou Yanjie Not Applicable
[4/4] irqchip: Ingenic: Add support for TCU of X1000. [1/4] dt-bindings: timer: Add X1000 bindings. 1 - - --- 2020-02-19 Zhou Yanjie Not Applicable
[v6,1/7] clk: JZ4780: Add function for enable the second core. Introduce SMP support for CI20 (based on JZ4780). - 1 2 --- 2020-02-20 Zhou Yanjie Accepted
[v6,2/7] MIPS: JZ4780: Introduce SMP support. Introduce SMP support for CI20 (based on JZ4780). - 1 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[v6,3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP. Introduce SMP support for CI20 (based on JZ4780). - - 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[v6,4/7] clocksource: Ingenic: Add high resolution timer support for SMP. Introduce SMP support for CI20 (based on JZ4780). - - 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[v6,5/7] dt-bindings: MIPS: Document Ingenic SoCs binding. Introduce SMP support for CI20 (based on JZ4780). - - 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[v6,6/7] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs. Introduce SMP support for CI20 (based on JZ4780). - - 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[v6,7/7] MIPS: CI20: Update defconfig to support SMP. Introduce SMP support for CI20 (based on JZ4780). - - 2 --- 2020-02-20 Zhou Yanjie Not Applicable
[RESEND] clk: Ingenic: Add support for TCU of X1000. [RESEND] clk: Ingenic: Add support for TCU of X1000. - - - --- 2020-03-17 Zhou Yanjie Accepted
[v6,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. [v6,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-03-22 Zhou Yanjie Superseded
[v6,2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830. [v6,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-03-22 Zhou Yanjie Superseded
[v6,3/6] dt-bindings: clock: Add X1830 bindings. [v6,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - 1 - --- 2020-03-22 Zhou Yanjie Superseded
[v6,4/6] clk: Ingenic: Add CGU driver for X1830. [v6,1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. - - - --- 2020-03-22 Zhou Yanjie Superseded
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