Show patches with: Submitter = Jerome Brunet       |    Archived = No       |   129 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,1/8] dt-bindings: clock: gxbb: expose spdif clock gates - - - --- 2017-03-28 Jerome Brunet Superseded
[RFC,7/7] clk: fix incorrect usage of ENOSYS - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,6/7] clk: cosmetic changes to clk_summary debugfs entry - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,5/7] clk: rollback set_rate_range changes on failure - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,4/7] clk: add support for clock protection - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,3/7] clk: rework calls to round and determine rate callbacks - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,2/7] clk: add set_phase core function - - - --- 2017-03-21 Jerome Brunet Superseded
[RFC,1/7] clk: take the prepare lock out of clk_core_set_parent - - - --- 2017-03-21 Jerome Brunet Superseded
[v2,9/9] dt-bindings: clk: gxbb: expose i2s output clock gates - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,8/9] clk: meson: mpll: correct N2 maximum value - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,7/9] clk: meson8b: add the mplls clocks 0, 1 and 2 - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,6/9] clk: meson: gxbb: mpll: use rw operation - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,5/9] clk: meson: mpll: add rw operation - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,4/9] clk: gxbb: put dividers and muxes in tables - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,3/9] clk: meson8b: put dividers and muxes in tables - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,2/9] clk: meson: add missing const qualifiers on gate arrays - - - --- 2017-03-09 Jerome Brunet Accepted
[v2,1/9] clk: meson: fix SET_PARM macro - 1 - --- 2017-03-09 Jerome Brunet Accepted
[RFC,2/2] clk: use enable_count to check if clk is busy - - - --- 2017-03-02 Jerome Brunet Superseded
[RFC,1/2] clk: fix CLK_SET_RATE_GATE on parent clocks - - - --- 2017-03-02 Jerome Brunet Superseded
[7/7] dt-bindings: clk: gxbb: expose i2s output clock gates - - - --- 2017-02-28 Jerome Brunet Superseded
[6/7] clk: meson: mpll: correct N2 maximum value - - - --- 2017-02-28 Jerome Brunet Superseded
[5/7] clk: meson8b: add the mplls clocks 0, 1 and 2 - - - --- 2017-02-28 Jerome Brunet Superseded
[4/7] clk: meson: gxbb: mpll: use rw operation - - - --- 2017-02-28 Jerome Brunet Superseded
[3/7] clk: meson: mpll: add rw operation - - - --- 2017-02-28 Jerome Brunet Superseded
[2/7] clk: gxbb: put dividers and muxes in tables - - - --- 2017-02-28 Jerome Brunet Superseded
[1/7] clk: meson8b: put dividers and muxes in tables - - - --- 2017-02-28 Jerome Brunet Superseded
clk: meson: fix SET_PARM macro - 1 - --- 2017-02-28 Jerome Brunet Superseded
clk: gxbb: fix CLKID_ETH defined twice 1 - - --- 2017-01-26 Jerome Brunet Accepted
clk: meson8b: fix clk81 register address - - - --- 2017-01-25 Jerome Brunet sboyd Accepted
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