diff mbox series

[04/15] dt-bindings: power: Add r8a779h0 SYSC power domain definitions

Message ID 1285e6a9fb423c8d6fff0c7faef157a1ea172d70.1704726960.git.geert+renesas@glider.be (mailing list archive)
State Not Applicable, archived
Headers show
Series arm64: renesas: Add R-Car V4M and Gray Hawk Single support | expand

Commit Message

Geert Uytterhoeven Jan. 8, 2024, 3:33 p.m. UTC
From: Duy Nguyen <duy.nguyen.rh@renesas.com>

Add power domain indices for the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 include/dt-bindings/power/r8a779h0-sysc.h | 49 +++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h

Comments

Niklas Söderlund Jan. 10, 2024, 12:04 p.m. UTC | #1
Hello Geert,

Thanks for your work.

On 2024-01-08 16:33:43 +0100, Geert Uytterhoeven wrote:
> From: Duy Nguyen <duy.nguyen.rh@renesas.com>
> 
> Add power domain indices for the Renesas R-Car V4M (R8A779H0) SoC.
> 
> Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
>  include/dt-bindings/power/r8a779h0-sysc.h | 49 +++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h
> 
> diff --git a/include/dt-bindings/power/r8a779h0-sysc.h b/include/dt-bindings/power/r8a779h0-sysc.h
> new file mode 100644
> index 0000000000000000..29f05f0401a13336
> --- /dev/null
> +++ b/include/dt-bindings/power/r8a779h0-sysc.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
> +#define __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
> +
> +/*
> + * These power domain indices match the Power Domain Register Numbers (PDR)
> + */
> +
> +#define R8A779H0_PD_A1E0D0C0		0
> +#define R8A779H0_PD_A1E0D0C1		1
> +#define R8A779H0_PD_A1E0D0C2		2
> +#define R8A779H0_PD_A1E0D0C3		3
> +#define R8A779H0_PD_A2E0D0		16
> +#define R8A779H0_PD_A3CR0		21
> +#define R8A779H0_PD_A3CR1		22
> +#define R8A779H0_PD_A3CR2		23
> +#define R8A779H0_PD_A33DGA		24
> +#define R8A779H0_PD_A23DGB		25
> +#define R8A779H0_PD_C4			31
> +#define R8A779H0_PD_A1DSP0		33
> +#define R8A779H0_PD_A2IMP01		34
> +#define R8A779H0_PD_A2PSC		35
> +#define R8A779H0_PD_A2CV0		36
> +#define R8A779H0_PD_A2CV1		37
> +#define R8A779H0_PD_A3IMR0		38
> +#define R8A779H0_PD_A3IMR1		39
> +#define R8A779H0_PD_A3VC		40
> +#define R8A779H0_PD_A2CN0		42
> +#define R8A779H0_PD_A1CN0		44
> +#define R8A779H0_PD_A1DSP1		45
> +#define R8A779H0_PD_A2DMA		47
> +#define R8A779H0_PD_A2CV2		48
> +#define R8A779H0_PD_A2CV3		49
> +#define R8A779H0_PD_A3IMR2		50
> +#define R8A779H0_PD_A3IMR3		51
> +#define R8A779H0_PD_A3PCI		52
> +#define R8A779H0_PD_A2PCIPHY		53
> +#define R8A779H0_PD_A3VIP0		56
> +#define R8A779H0_PD_A3VIP2		58
> +#define R8A779H0_PD_A3ISP0		60
> +#define R8A779H0_PD_A3DUL		62
> +
> +/* Always-on power area */
> +#define R8A779H0_PD_ALWAYS_ON		64
> +
> +#endif /* __DT_BINDINGS_POWER_R8A779H0_SYSC_H__ */
> -- 
> 2.34.1
> 
>
diff mbox series

Patch

diff --git a/include/dt-bindings/power/r8a779h0-sysc.h b/include/dt-bindings/power/r8a779h0-sysc.h
new file mode 100644
index 0000000000000000..29f05f0401a13336
--- /dev/null
+++ b/include/dt-bindings/power/r8a779h0-sysc.h
@@ -0,0 +1,49 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779H0_PD_A1E0D0C0		0
+#define R8A779H0_PD_A1E0D0C1		1
+#define R8A779H0_PD_A1E0D0C2		2
+#define R8A779H0_PD_A1E0D0C3		3
+#define R8A779H0_PD_A2E0D0		16
+#define R8A779H0_PD_A3CR0		21
+#define R8A779H0_PD_A3CR1		22
+#define R8A779H0_PD_A3CR2		23
+#define R8A779H0_PD_A33DGA		24
+#define R8A779H0_PD_A23DGB		25
+#define R8A779H0_PD_C4			31
+#define R8A779H0_PD_A1DSP0		33
+#define R8A779H0_PD_A2IMP01		34
+#define R8A779H0_PD_A2PSC		35
+#define R8A779H0_PD_A2CV0		36
+#define R8A779H0_PD_A2CV1		37
+#define R8A779H0_PD_A3IMR0		38
+#define R8A779H0_PD_A3IMR1		39
+#define R8A779H0_PD_A3VC		40
+#define R8A779H0_PD_A2CN0		42
+#define R8A779H0_PD_A1CN0		44
+#define R8A779H0_PD_A1DSP1		45
+#define R8A779H0_PD_A2DMA		47
+#define R8A779H0_PD_A2CV2		48
+#define R8A779H0_PD_A2CV3		49
+#define R8A779H0_PD_A3IMR2		50
+#define R8A779H0_PD_A3IMR3		51
+#define R8A779H0_PD_A3PCI		52
+#define R8A779H0_PD_A2PCIPHY		53
+#define R8A779H0_PD_A3VIP0		56
+#define R8A779H0_PD_A3VIP2		58
+#define R8A779H0_PD_A3ISP0		60
+#define R8A779H0_PD_A3DUL		62
+
+/* Always-on power area */
+#define R8A779H0_PD_ALWAYS_ON		64
+
+#endif /* __DT_BINDINGS_POWER_R8A779H0_SYSC_H__ */