From patchwork Fri Apr 22 10:31:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Penny Chiu X-Patchwork-Id: 8909341 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 954F0BF29F for ; Fri, 22 Apr 2016 10:34:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8FD0A201F2 for ; Fri, 22 Apr 2016 10:34:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 265992025A for ; Fri, 22 Apr 2016 10:34:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752424AbcDVKcb (ORCPT ); Fri, 22 Apr 2016 06:32:31 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5909 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752388AbcDVKc1 (ORCPT ); Fri, 22 Apr 2016 06:32:27 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 22 Apr 2016 03:32:22 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 22 Apr 2016 03:32:11 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Apr 2016 03:32:11 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 22 Apr 2016 10:32:21 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 22 Apr 2016 10:32:21 +0000 Received: from pchiu-i7.nvidia.com (Not Verified[10.19.120.104]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 22 Apr 2016 03:32:21 -0700 From: Penny Chiu To: , , , , , , CC: , , , , , , , , Penny Chiu Subject: [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Date: Fri, 22 Apr 2016 18:31:04 +0800 Message-ID: <1461321071-6431-5-git-send-email-pchiu@nvidia.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> References: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add Tegra210 support and related CVB table in tegra124 DFLL driver, and also update the binding document. Signed-off-by: Penny Chiu --- .../bindings/clock/nvidia,tegra124-dfll.txt | 4 +- drivers/clk/tegra/Makefile | 4 +- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 55 ++++++++++++++++++++++ 3 files changed, 61 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 84080a8..42a1fe6 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -11,7 +11,9 @@ communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Currently only the I2C mode is supported by these bindings. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of following: + - "nvidia,tegra124-dfll" for the Tegra124 SoC + - "nvidia,tegra210-dfll" for the Tegra210 SoC - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic. diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 97984c5..9b8e9de 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -17,7 +17,9 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o +ifneq ($(filter y, $(CONFIG_ARCH_TEGRA_124_SOC) $(CONFIG_ARCH_TEGRA_210_SOC)),) +obj-y += clk-tegra124-dfll-fcpu.o +endif obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index b577bc6..6b3316c 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -44,6 +44,11 @@ static const unsigned long tegra124_cpu_max_freq_table[] = { [3] = 2524500000UL, }; +static const unsigned long tegra210_cpu_max_freq_table[] = { + [0] = 1912500000UL, + [1] = 1912500000UL, +}; + static const struct cvb_table tegra124_cpu_cvb_tables[] = { { .speedo_id = -1, @@ -87,6 +92,45 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, }; +static const struct cvb_table tegra210_cpu_cvb_tables[] = { + { + .speedo_id = -1, + .process_id = -1, + .min_millivolts = 850, + .max_millivolts = 1170, + .speedo_scale = 100, + .voltage_scale = 1000, + .cvb_table = { + {51000000UL, {1007452, -23865, 370} }, + {102000000UL, {1007452, -23865, 370} }, + {204000000UL, {1007452, -23865, 370} }, + {306000000UL, {1052709, -24875, 370} }, + {408000000UL, {1099069, -25895, 370} }, + {510000000UL, {1146534, -26905, 370} }, + {612000000UL, {1195102, -27915, 370} }, + {714000000UL, {1244773, -28925, 370} }, + {816000000UL, {1295549, -29935, 370} }, + {918000000UL, {1347428, -30955, 370} }, + {1020000000UL, {1400411, -31965, 370} }, + {1122000000UL, {1454497, -32975, 370} }, + {1224000000UL, {1509687, -33985, 370} }, + {1326000000UL, {1565981, -35005, 370} }, + {1428000000UL, {1623379, -36015, 370} }, + {1530000000UL, {1681880, -37025, 370} }, + {1632000000UL, {1741485, -38035, 370} }, + {1734000000UL, {1802194, -39055, 370} }, + {1836000000UL, {1864006, -40065, 370} }, + {1912500000UL, {1910780, -40815, 370} }, + {0, { 0, 0, 0} }, + }, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -94,11 +138,22 @@ static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) }; +static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = { + .cpu_max_freq_table = tegra210_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table), + .cpu_cvb_tables = tegra210_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables) +}; + static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { { .compatible = "nvidia,tegra124-dfll", .data = &tegra124_dfll_fcpu_data }, + { + .compatible = "nvidia,tegra210-dfll", + .data = &tegra210_dfll_fcpu_data + }, { }, }; MODULE_DEVICE_TABLE(of, tegra124_dfll_fcpu_of_match);