From patchwork Thu Apr 28 13:11:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 8970011 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C962B9F1C1 for ; Thu, 28 Apr 2016 13:11:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A7A3B202A1 for ; Thu, 28 Apr 2016 13:11:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 85CCF202C8 for ; Thu, 28 Apr 2016 13:11:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751710AbcD1NLY (ORCPT ); Thu, 28 Apr 2016 09:11:24 -0400 Received: from gloria.sntech.de ([95.129.55.99]:40522 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751435AbcD1NLX (ORCPT ); Thu, 28 Apr 2016 09:11:23 -0400 Received: from ip9234b7c8.dynamic.kabel-deutschland.de ([146.52.183.200] helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1avliy-0006x7-PT; Thu, 28 Apr 2016 15:11:21 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner Subject: [PATCH 4/7] clk: rockchip: abstract pll get-params and set-params operations Date: Thu, 28 Apr 2016 15:11:12 +0200 Message-Id: <1461849075-8310-5-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461849075-8310-1-git-send-email-heiko@sntech.de> References: <1461849075-8310-1-git-send-email-heiko@sntech.de> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This moves the pll-specific get_params and set_params functions into a per-pll struct that gets associated at init time and will help us reign in some code duplication we're faced with right now. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 54 ++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index e56637d..2c30f52 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -30,6 +30,14 @@ #define PLL_MODE_NORM 0x1 #define PLL_MODE_DEEP 0x2 +struct rockchip_clk_pll; +struct rockchip_pll_data { + void (*get_params)(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate); + int (*set_params)(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate); +}; + struct rockchip_clk_pll { struct clk_hw hw; @@ -48,6 +56,7 @@ struct rockchip_clk_pll { spinlock_t *lock; struct rockchip_clk_provider *ctx; + const struct rockchip_pll_data *data; }; #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) @@ -164,7 +173,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, struct rockchip_pll_rate_table cur; u64 rate64 = prate; - rockchip_rk3036_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); rate64 *= cur.fbdiv; do_div(rate64, cur.refdiv); @@ -259,7 +268,7 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - return rockchip_rk3036_pll_set_params(pll, rate); + return pll->data->set_params(pll, rate); } static int rockchip_rk3036_pll_enable(struct clk_hw *hw) @@ -306,7 +315,7 @@ static void rockchip_rk3036_pll_init(struct clk_hw *hw) if (!rate) return; - rockchip_rk3036_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), drate); @@ -330,10 +339,15 @@ static void rockchip_rk3036_pll_init(struct clk_hw *hw) pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", __func__, __clk_get_name(hw->clk)); - rockchip_rk3036_pll_set_params(pll, rate); + pll->data->set_params(pll, rate); } } +static const struct rockchip_pll_data rockchip_rk3036_pll_data = { + .get_params = rockchip_rk3036_pll_get_params, + .set_params = rockchip_rk3036_pll_set_params, +}; + static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { .recalc_rate = rockchip_rk3036_pll_recalc_rate, .enable = rockchip_rk3036_pll_enable, @@ -405,7 +419,7 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, return prate; } - rockchip_rk3066_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); rate64 *= cur.nf; do_div(rate64, cur.nr); @@ -490,7 +504,7 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - return rockchip_rk3066_pll_set_params(pll, rate); + return pll->data->set_params(pll, rate); } static int rockchip_rk3066_pll_enable(struct clk_hw *hw) @@ -537,7 +551,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) if (!rate) return; - rockchip_rk3066_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, @@ -546,10 +560,15 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) || rate->nb != cur.nb) { pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", __func__, clk_hw_get_name(hw)); - rockchip_rk3066_pll_set_params(pll, rate); + pll->data->set_params(pll, rate); } } +static const struct rockchip_pll_data rockchip_rk3066_pll_data = { + .get_params = rockchip_rk3066_pll_get_params, + .set_params = rockchip_rk3066_pll_set_params, +}; + static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { .recalc_rate = rockchip_rk3066_pll_recalc_rate, .enable = rockchip_rk3066_pll_enable, @@ -638,7 +657,7 @@ static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, struct rockchip_pll_rate_table cur; u64 rate64 = prate; - rockchip_rk3399_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); rate64 *= cur.fbdiv; do_div(rate64, cur.refdiv); @@ -735,7 +754,7 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - return rockchip_rk3399_pll_set_params(pll, rate); + return pll->data->set_params(pll, rate); } static int rockchip_rk3399_pll_enable(struct clk_hw *hw) @@ -782,7 +801,7 @@ static void rockchip_rk3399_pll_init(struct clk_hw *hw) if (!rate) return; - rockchip_rk3399_pll_get_params(pll, &cur); + pll->data->get_params(pll, &cur); pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), drate); @@ -806,10 +825,15 @@ static void rockchip_rk3399_pll_init(struct clk_hw *hw) pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", __func__, __clk_get_name(hw->clk)); - rockchip_rk3399_pll_set_params(pll, rate); + pll->data->set_params(pll, rate); } } +static const struct rockchip_pll_data rockchip_rk3399_pll_data = { + .get_params = rockchip_rk3399_pll_get_params, + .set_params = rockchip_rk3399_pll_set_params, +}; + static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { .recalc_rate = rockchip_rk3399_pll_recalc_rate, .enable = rockchip_rk3399_pll_enable, @@ -916,18 +940,24 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, switch (pll_type) { case pll_rk3036: + pll->data = &rockchip_rk3036_pll_data; + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3036_pll_clk_norate_ops; else init.ops = &rockchip_rk3036_pll_clk_ops; break; case pll_rk3066: + pll->data = &rockchip_rk3066_pll_data; + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; break; case pll_rk3399: + pll->data = &rockchip_rk3399_pll_data; + if (!pll->rate_table) init.ops = &rockchip_rk3399_pll_clk_norate_ops; else