From patchwork Thu Apr 28 13:11:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 8970041 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0F579BF29F for ; Thu, 28 Apr 2016 13:11:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E3374202C8 for ; Thu, 28 Apr 2016 13:11:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 09EB2202A1 for ; Thu, 28 Apr 2016 13:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751112AbcD1NLZ (ORCPT ); Thu, 28 Apr 2016 09:11:25 -0400 Received: from gloria.sntech.de ([95.129.55.99]:40547 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751411AbcD1NLY (ORCPT ); Thu, 28 Apr 2016 09:11:24 -0400 Received: from ip9234b7c8.dynamic.kabel-deutschland.de ([146.52.183.200] helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1avlj0-0006x7-Hq; Thu, 28 Apr 2016 15:11:22 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner Subject: [PATCH 7/7] clk: rockchip: fold pll init functions into a common one Date: Thu, 28 Apr 2016 15:11:15 +0200 Message-Id: <1461849075-8310-8-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461849075-8310-1-git-send-email-heiko@sntech.de> References: <1461849075-8310-1-git-send-email-heiko@sntech.de> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The pll init functions are now all the same, so we can generalize them into one common function used by all to save some duplication. The parent-check in the original functions does not do anything useful at all, as we're not doing any real rate-handling at this point anymore, so can just go away. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 125 ++++++++++------------------------------- 1 file changed, 29 insertions(+), 96 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 5bd0545..1223eee 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -117,6 +117,32 @@ static int rockchip_pll_set_rate(struct clk_hw *hw, unsigned long drate, return pll->data->set_params(pll, rate); } +static void rockchip_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return; + + pll->data->get_params(pll, &cur); + + if (!pll->data->compare_params(pll, rate, &cur)) { + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + pll->data->set_params(pll, rate); + } +} + /* * Wait for the pll to reach the locked state. * The calling set_rate function is responsible for making sure the @@ -320,39 +346,6 @@ static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) return !(pllcon & RK3036_PLLCON1_PWRDOWN); } -static void rockchip_rk3036_pll_init(struct clk_hw *hw) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - struct rockchip_pll_rate_table cur; - unsigned long drate; - - if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) - return; - - drate = clk_hw_get_rate(hw); - rate = rockchip_get_pll_settings(pll, drate); - - /* when no rate setting for the current rate, rely on clk_set_rate */ - if (!rate) - return; - - pll->data->get_params(pll, &cur); - if (!pll->data->compare_params(pll, rate, &cur)) { - struct clk *parent = clk_get_parent(hw->clk); - - if (!parent) { - pr_warn("%s: parent of %s not available\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", - __func__, __clk_get_name(hw->clk)); - pll->data->set_params(pll, rate); - } -} - static const struct rockchip_pll_data rockchip_rk3036_pll_data = { .get_params = rockchip_rk3036_pll_get_params, .set_params = rockchip_rk3036_pll_set_params, @@ -373,7 +366,7 @@ static const struct clk_ops rockchip_rk3036_pll_clk_ops = { .enable = rockchip_rk3036_pll_enable, .disable = rockchip_rk3036_pll_disable, .is_enabled = rockchip_rk3036_pll_is_enabled, - .init = rockchip_rk3036_pll_init, + .init = rockchip_pll_init, }; /** @@ -539,32 +532,6 @@ static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) return !(pllcon & RK3066_PLLCON3_PWRDOWN); } -static void rockchip_rk3066_pll_init(struct clk_hw *hw) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - struct rockchip_pll_rate_table cur; - unsigned long drate; - - if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) - return; - - drate = clk_hw_get_rate(hw); - rate = rockchip_get_pll_settings(pll, drate); - - /* when no rate setting for the current rate, rely on clk_set_rate */ - if (!rate) - return; - - pll->data->get_params(pll, &cur); - - if (!pll->data->compare_params(pll, rate, &cur)) { - pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", - __func__, clk_hw_get_name(hw)); - pll->data->set_params(pll, rate); - } -} - static const struct rockchip_pll_data rockchip_rk3066_pll_data = { .get_params = rockchip_rk3066_pll_get_params, .set_params = rockchip_rk3066_pll_set_params, @@ -585,7 +552,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { .enable = rockchip_rk3066_pll_enable, .disable = rockchip_rk3066_pll_disable, .is_enabled = rockchip_rk3066_pll_is_enabled, - .init = rockchip_rk3066_pll_init, + .init = rockchip_pll_init, }; /** @@ -785,40 +752,6 @@ static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) return !(pllcon & RK3399_PLLCON3_PWRDOWN); } -static void rockchip_rk3399_pll_init(struct clk_hw *hw) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - struct rockchip_pll_rate_table cur; - unsigned long drate; - - if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) - return; - - drate = clk_hw_get_rate(hw); - rate = rockchip_get_pll_settings(pll, drate); - - /* when no rate setting for the current rate, rely on clk_set_rate */ - if (!rate) - return; - - pll->data->get_params(pll, &cur); - - if (!pll->data->compare_params(pll, rate, &cur)) { - struct clk *parent = clk_get_parent(hw->clk); - - if (!parent) { - pr_warn("%s: parent of %s not available\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", - __func__, __clk_get_name(hw->clk)); - pll->data->set_params(pll, rate); - } -} - static const struct rockchip_pll_data rockchip_rk3399_pll_data = { .get_params = rockchip_rk3399_pll_get_params, .set_params = rockchip_rk3399_pll_set_params, @@ -839,7 +772,7 @@ static const struct clk_ops rockchip_rk3399_pll_clk_ops = { .enable = rockchip_rk3399_pll_enable, .disable = rockchip_rk3399_pll_disable, .is_enabled = rockchip_rk3399_pll_is_enabled, - .init = rockchip_rk3399_pll_init, + .init = rockchip_pll_init, }; /*