From patchwork Thu May 5 15:53:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Sperl X-Patchwork-Id: 9025571 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D9DCC9F6E1 for ; Thu, 5 May 2016 15:53:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F224D203AE for ; Thu, 5 May 2016 15:53:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F064B203B0 for ; Thu, 5 May 2016 15:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757620AbcEEPxj (ORCPT ); Thu, 5 May 2016 11:53:39 -0400 Received: from 212-186-180-163.dynamic.surfer.at ([212.186.180.163]:53476 "EHLO cgate.sperl.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757365AbcEEPxi (ORCPT ); Thu, 5 May 2016 11:53:38 -0400 Received: from rasp3a.intern.sperl.org (account martin@sperl.org [10.10.10.43] verified) by sperl.org (CommuniGate Pro SMTP 6.1.2) with ESMTPSA id 6448385; Thu, 05 May 2016 15:53:31 +0000 From: kernel@martin.sperl.org To: Rob Herring , Mark Rutland , Stephen Warren , Lee Jones , Eric Anholt , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: Martin Sperl Subject: [PATCH 2/5] clk: bcm2835: expose the parent clocks via include/dt-bindings Date: Thu, 5 May 2016 15:53:25 +0000 Message-Id: <1462463608-22940-3-git-send-email-kernel@martin.sperl.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462463608-22940-1-git-send-email-kernel@martin.sperl.org> References: <1462463608-22940-1-git-send-email-kernel@martin.sperl.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Martin Sperl Expose the parent clocks via include/dt-bindings, so that they can easily get referred to in the device tree. Signed-off-by: Martin Sperl --- drivers/clk/bcm/clk-bcm2835.c | 45 ++++++++++++++++++------------------- include/dt-bindings/clock/bcm2835.h | 26 +++++++++++++++++++++ 2 files changed, 48 insertions(+), 23 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index c19b99c9..1b1657d 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1303,10 +1303,10 @@ struct bcm2835_clk_desc { /* main oscillator parent mux */ static const char *const bcm2835_clock_osc_parents[] = { - "gnd", - "xosc", - "testdebug0", - "testdebug1" + [BCM2835_OSC_PARENT_GND] = "gnd", + [BCM2835_OSC_PARENT_OSC] = "xosc", + [BCM2835_OSC_PARENT_TESTDEBUG0] = "testdebug0", + [BCM2835_OSC_PARENT_TESTDEBUG1] = "testdebug1", }; #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ @@ -1316,14 +1316,14 @@ static const char *const bcm2835_clock_osc_parents[] = { /* main peripherial parent mux */ static const char *const bcm2835_clock_per_parents[] = { - "gnd", - "xosc", - "testdebug0", - "testdebug1", - "plla_per", - "pllc_per", - "plld_per", - "pllh_aux", + [BCM2835_PER_PARENT_GND] = "gnd", + [BCM2835_PER_PARENT_OSC] = "xosc", + [BCM2835_PER_PARENT_TESTDEBUG0] = "testdebug0", + [BCM2835_PER_PARENT_TESTDEBUG1] = "testdebug1", + [BCM2835_PER_PARENT_PLLA_PER] = "plla_per", + [BCM2835_PER_PARENT_PLLC_PER] = "pllc_per", + [BCM2835_PER_PARENT_PLLD_PER] = "plld_per", + [BCM2835_PER_PARENT_PLLH_AUX] = "pllh_aux", }; #define REGISTER_PER_CLK(...) REGISTER_CLK( \ @@ -1333,18 +1333,17 @@ static const char *const bcm2835_clock_per_parents[] = { /* main vpu parent mux */ static const char *const bcm2835_clock_vpu_parents[] = { - "gnd", - "xosc", - "testdebug0", - "testdebug1", - "plla_core", - "pllc_core0", - "plld_core", - "pllh_aux", - "pllc_core1", - "pllc_core2", + [BCM2835_VPU_PARENT_GND] = "gnd", + [BCM2835_VPU_PARENT_OSC] = "xosc", + [BCM2835_VPU_PARENT_TESTDEBUG0] = "testdebug0", + [BCM2835_VPU_PARENT_TESTDEBUG1] = "testdebug1", + [BCM2835_VPU_PARENT_PLLA_CORE] = "plla_core", + [BCM2835_VPU_PARENT_PLLC_CORE0] = "pllc_core0", + [BCM2835_VPU_PARENT_PLLD_CORE] = "plld_core", + [BCM2835_VPU_PARENT_PLLH_AUX] = "pllh_aux", + [BCM2835_VPU_PARENT_PLLC_CORE1] = "pllc_core1", + [BCM2835_VPU_PARENT_PLLC_CORE2] = "pllc_core2", }; - #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ .parents = bcm2835_clock_vpu_parents, \ diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 360e00c..e5396fe 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -64,3 +64,29 @@ #define BCM2835_CLOCK_CAM1 46 #define BCM2835_CLOCK_DSI0E 47 #define BCM2835_CLOCK_DSI1E 48 + +/* the parent clock for different clock types */ +#define BCM2835_OSC_PARENT_GND 0 +#define BCM2835_OSC_PARENT_OSC 1 +#define BCM2835_OSC_PARENT_TESTDEBUG0 2 +#define BCM2835_OSC_PARENT_TESTDEBUG1 3 + +#define BCM2835_PER_PARENT_GND 0 +#define BCM2835_PER_PARENT_OSC 1 +#define BCM2835_PER_PARENT_TESTDEBUG0 2 +#define BCM2835_PER_PARENT_TESTDEBUG1 3 +#define BCM2835_PER_PARENT_PLLA_PER 4 +#define BCM2835_PER_PARENT_PLLC_PER 5 +#define BCM2835_PER_PARENT_PLLD_PER 6 +#define BCM2835_PER_PARENT_PLLH_AUX 7 + +#define BCM2835_VPU_PARENT_GND 0 +#define BCM2835_VPU_PARENT_OSC 1 +#define BCM2835_VPU_PARENT_TESTDEBUG0 2 +#define BCM2835_VPU_PARENT_TESTDEBUG1 3 +#define BCM2835_VPU_PARENT_PLLA_CORE 4 +#define BCM2835_VPU_PARENT_PLLC_CORE0 5 +#define BCM2835_VPU_PARENT_PLLD_CORE 6 +#define BCM2835_VPU_PARENT_PLLH_AUX 7 +#define BCM2835_VPU_PARENT_PLLC_CORE1 8 +#define BCM2835_VPU_PARENT_PLLC_CORE2 9