From patchwork Sun May 8 20:01:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9040131 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A9AC09F30C for ; Sun, 8 May 2016 20:02:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9C5892010E for ; Sun, 8 May 2016 20:02:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6F1692013D for ; Sun, 8 May 2016 20:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750977AbcEHUCT (ORCPT ); Sun, 8 May 2016 16:02:19 -0400 Received: from down.free-electrons.com ([37.187.137.238]:48080 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751063AbcEHUCS (ORCPT ); Sun, 8 May 2016 16:02:18 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 5A29C20C; Sun, 8 May 2016 22:02:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (LFbn-1-2034-31.w90-76.abo.wanadoo.fr [90.76.103.31]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5C3D0B53; Sun, 8 May 2016 22:02:00 +0200 (CEST) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , Chen-Yu Tsai Cc: linux-clk@vger.kernel.org, Hans de Goede , Andre Przywara , Rob Herring , Vishnu Patekar , linux-arm-kernel@lists.infradead.org, Boris Brezillon , Maxime Ripard Subject: [PATCH 08/16] clk: sunxi-ng: Add M-factor clock support Date: Sun, 8 May 2016 22:01:43 +0200 Message-Id: <1462737711-10017-9-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1462737711-10017-1-git-send-email-maxime.ripard@free-electrons.com> References: <1462737711-10017-1-git-send-email-maxime.ripard@free-electrons.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce support for clocks that divide by a linear factor. Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_m.c | 135 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_m.h | 101 +++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu_m.c create mode 100644 drivers/clk/sunxi-ng/ccu_m.h diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a47a3bbdf285..f41de901c607 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -4,5 +4,6 @@ obj-y += ccu_reset.o obj-y += ccu_div_table.o obj-y += ccu_fixed_factor.o obj-y += ccu_gate.o +obj-y += ccu_m.o obj-y += ccu_mux.o obj-y += ccu_phase.o diff --git a/drivers/clk/sunxi-ng/ccu_m.c b/drivers/clk/sunxi-ng/ccu_m.c new file mode 100644 index 000000000000..424eb6da0d5b --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include + +#include "ccu_gate.h" +#include "ccu_m.h" +#include "ccu_mux.h" + +static void ccu_m_find_best(unsigned long parent, unsigned long rate, + unsigned int max_m, unsigned int *m) +{ + unsigned int _m = parent / rate; + + if (_m > max_m) + _m = max_m; + + *m = _m; +} + +static unsigned long ccu_m_round_rate(struct ccu_mux_internal *mux, + unsigned long parent_rate, + unsigned long rate, + void *data) +{ + struct ccu_m *cm = data; + unsigned int m; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + return parent_rate / m; +} + + +static void ccu_m_disable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_disable(&cm->common, cm->enable); +} + +static int ccu_m_enable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_enable(&cm->common, cm->enable); +} + +static int ccu_m_is_enabled(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_is_enabled(&cm->common, cm->enable); +} + +static unsigned long ccu_m_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long m; + u32 reg; + + reg = readl(cm->common.base + cm->common.reg); + + m = reg >> cm->m.shift; + m &= (1 << cm->m.width) - 1; + + return parent_rate / (m + 1); +} + +static int ccu_m_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_determine_rate(&cm->common, &cm->mux, + req, ccu_m_round_rate, cm); +} + +static int ccu_m_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long flags; + unsigned int m; + u32 reg; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + spin_lock_irqsave(cm->common.lock, flags); + + reg = readl(cm->common.base + cm->common.reg); + reg &= ((1 << cm->m.width) - 1) << cm->m.shift; + + writel(reg | ((m - 1) << cm->m.shift), + cm->common.base + cm->common.reg); + + spin_unlock_irqrestore(cm->common.lock, flags); + + return 0; +} + +static u8 ccu_m_get_parent(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_get_parent(&cm->common, &cm->mux); +} + +static int ccu_m_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); +} + +const struct clk_ops ccu_m_ops = { + .disable = ccu_m_disable, + .enable = ccu_m_enable, + .is_enabled = ccu_m_is_enabled, + + .get_parent = ccu_m_get_parent, + .set_parent = ccu_m_set_parent, + + .determine_rate = ccu_m_determine_rate, + .recalc_rate = ccu_m_recalc_rate, + .set_rate = ccu_m_set_rate, +}; diff --git a/drivers/clk/sunxi-ng/ccu_m.h b/drivers/clk/sunxi-ng/ccu_m.h new file mode 100644 index 000000000000..625c0a7cef43 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_M_H_ +#define _CCU_M_H_ + +#include + +#include "ccu_common.h" +#include "ccu_factor.h" +#include "ccu_mux.h" + +struct ccu_m { + u32 enable; + + struct ccu_factor m; + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, \ + _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_m *hw_to_ccu_m(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_m, common); +} + +extern const struct clk_ops ccu_m_ops; + +#endif /* _CCU_M_H_ */