From patchwork Mon May 9 12:31:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 9046021 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6EF439F30C for ; Mon, 9 May 2016 12:32:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5EFB720148 for ; Mon, 9 May 2016 12:32:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 502162012D for ; Mon, 9 May 2016 12:32:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751741AbcEIMcZ (ORCPT ); Mon, 9 May 2016 08:32:25 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:36565 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751962AbcEIMcY (ORCPT ); Mon, 9 May 2016 08:32:24 -0400 Received: by mail-pa0-f45.google.com with SMTP id bt5so71873222pac.3 for ; Mon, 09 May 2016 05:32:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6u99OSoHM6ehffeKnUQK5Wtg46Qc60D4ebj+2zOlsho=; b=CjuBvmssQD/FjZ4Guk0FJa3xlpJLbkS1hR/07lMSEMUii2jALI8Yb2XXHCI4qBeMsh gaYpWAezZJmv0NtoruVjjj2LjHXDFdYhvyQc4a4zFMB24xU6NcbnhVh9iQjM3H+67Ev2 juzeTaHDBHch27ivTN4VEN/1tdYfYL8BhX13M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6u99OSoHM6ehffeKnUQK5Wtg46Qc60D4ebj+2zOlsho=; b=eXrUFfLbMUVB17PhVDNX3+oAC0DLj+OQLXz7Az7IeF7HaZWgXIaYj3NrYPbmqePECe m8/bHri3gdxSRkeIIjCAPVGT91vkbw/FGV9un7+haq5KDYPocDrwflODhuszqj0a2hK3 +cVlhq5zebDVsJJtk26LG51KSewY8Y9OYwNtywnDB3ofAUZ88VvQkC3caz77t497WA7P 4XP/Jwsk4TiGPGtSHKUF7yGQ8u7tG1b/4a3UHaGs98FabyeOtAag8eDGPIPN109vA+QL 99uTO2Z0ovYH646Mq/h/fsUT5e7wlk8bq5c02U4D5km37ILXpIUta9RPm0ghO9lwqN1O Ms1w== X-Gm-Message-State: AOPr4FU7DK0pHBeIAPRsCd2RbrggTAZOiz5UqZQX6kr6/7/0Z3NGLE2QjNo66rxpc+eukA== X-Received: by 10.67.22.129 with SMTP id hs1mr50178323pad.105.1462797143388; Mon, 09 May 2016 05:32:23 -0700 (PDT) Received: from icarus.au.ibm.com ([2403:480:11:10:3400:b218:cbe9:48cb]) by smtp.gmail.com with ESMTPSA id i75sm17021382pfj.51.2016.05.09.05.32.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 May 2016 05:32:22 -0700 (PDT) From: Joel Stanley To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jk@ozlabs.org, benh@kernel.crashing.org, arnd@arndb.de, heiko@sntech.de Subject: [PATCH 3/4] drvers/clk: Support fifth generation Aspeed SoCs Date: Mon, 9 May 2016 22:01:50 +0930 Message-Id: <1462797111-14271-4-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462797111-14271-1-git-send-email-joel@jms.id.au> References: <1462797111-14271-1-git-send-email-joel@jms.id.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A basic driver to create fixed rate clock devices from strapping registers. Like the ast2400, the ast2500 clocks are derived from an external oscillator and the frequency of this can be determined from the strapping of the processor. The frequency of internal clocks can be derived from other registers in the SCU (System Control Unit). The layout of the internal clocks is a bit different to the ast2400, as are the divisor reigisters, so it has it's own driver. Signed-off-by: Joel Stanley --- drivers/clk/aspeed/Makefile | 1 + drivers/clk/aspeed/clk-g5.c | 189 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+) create mode 100644 drivers/clk/aspeed/clk-g5.c diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index d3457fbe3019..9ddb0f8f4356 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_MACH_ASPEED_G4) += clk-g4.o +obj-$(CONFIG_MACH_ASPEED_G5) += clk-g5.o diff --git a/drivers/clk/aspeed/clk-g5.c b/drivers/clk/aspeed/clk-g5.c new file mode 100644 index 000000000000..812fd9accf30 --- /dev/null +++ b/drivers/clk/aspeed/clk-g5.c @@ -0,0 +1,189 @@ +/* + * Copyright 2016 IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +static void __init aspeed_of_clkin_clk_init(struct device_node *node) +{ + struct clk *clk; + void __iomem *base; + int reg, rate; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + /* Strap register SCU70 */ + reg = readl(base) & BIT(23); + iounmap(base); + + if (reg) + rate = 25 * 1000 * 1000; + else + rate = 24 * 1000 * 1000; + + clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_clkin_clock, "aspeed,g5-clkin-clock", + aspeed_of_clkin_clk_init); + + +static void __init aspeed_of_hpll_clk_init(struct device_node *node) +{ + struct clk *clk, *clkin_clk; + void __iomem *base; + int reg, rate, clkin; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + /* H-PLL parameter register SCU24 */ + reg = readl(base); + iounmap(base); + + clkin_clk = of_clk_get(node, 0); + if (IS_ERR(clkin_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + clkin = clk_get_rate(clkin_clk); + + if (reg & BIT(21)) { + rate = 0; + } else if (reg & BIT(20)) { + rate = clkin; + } else { + int p = (reg >> 13) & 0x3f; + int m = (reg >> 5) & 0xff; + int n = reg & 0x1f; + + rate = clkin * ((m + 1) / (n + 1)) / (p + 1); + } + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g5-hpll-clock", + aspeed_of_hpll_clk_init); + + +static void __init aspeed_of_ahb_clk_init(struct device_node *node) +{ + struct clk *clk, *hpll_clk; + void __iomem *base; + int reg, rate, hpll; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + /* Strap register SCU70 */ + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + reg = (readl(base) >> 9) & 0x03; + iounmap(base); + + /* A value of zero is undefined */ + WARN_ON(reg == 0); + + hpll_clk = of_clk_get(node, 0); + if (IS_ERR(hpll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + hpll = clk_get_rate(hpll_clk); + + rate = hpll / 2 / (reg + 1); + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_ahb_clock, "aspeed,g5-ahb-clock", + aspeed_of_ahb_clk_init); + + +static void __init aspeed_of_apb_clk_init(struct device_node *node) +{ + struct clk *clk, *hpll_clk; + void __iomem *base; + int reg, rate; + const char *name = node->name; + const char *parent_name; + + of_property_read_string(node, "clock-output-names", &name); + parent_name = of_clk_get_parent_name(node, 0); + + /* Clock selection register SCU08 */ + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + reg = readl(base) >> 23 & 0x3; + iounmap(base); + + hpll_clk = of_clk_get(node, 0); + if (IS_ERR(hpll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = clk_get_rate(hpll_clk) / (4 * (reg + 1)); + + clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g5-apb-clock", + aspeed_of_apb_clk_init);