From patchwork Wed May 11 12:01:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 9068781 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F349EBF29F for ; Wed, 11 May 2016 12:07:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D030E200B4 for ; Wed, 11 May 2016 12:07:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B0DF20154 for ; Wed, 11 May 2016 12:07:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751608AbcEKMCe (ORCPT ); Wed, 11 May 2016 08:02:34 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:31529 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750979AbcEKMCd (ORCPT ); Wed, 11 May 2016 08:02:33 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O7000EMUHG6J850@mailout3.w1.samsung.com>; Wed, 11 May 2016 13:02:30 +0100 (BST) X-AuditID: cbfec7f5-f792a6d000001302-4a-57331f56aaa2 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id EA.FA.04866.65F13375; Wed, 11 May 2016 13:02:30 +0100 (BST) Received: from AMDC2174.DIGITAL.local ([106.120.53.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O7000965HG0RB60@eusync3.samsung.com>; Wed, 11 May 2016 13:02:30 +0100 (BST) From: Krzysztof Kozlowski To: Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz Subject: [PATCH 03/18] clk: samsung: exynos3250: Constify all clock initializers Date: Wed, 11 May 2016 14:01:59 +0200 Message-id: <1462968134-6085-3-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1462968134-6085-1-git-send-email-k.kozlowski@samsung.com> References: <1462968134-6085-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDLMWRmVeSWpSXmKPExsVy+t/xq7ph8sbhBituMltsnLGe1eL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxeE37awWP850s1is2vWH0YHb4/2NVnaP y329TB47Z91l99i0qpPNY/OSeo++LasYPT5vkgtgj+KySUnNySxLLdK3S+DKuHffquCBTcX0 l0dYGxhPGnUxcnJICJhIvH98nR3CFpO4cG89G4gtJLCUUeLnC+MuRi4gu5FJ4vudZUwgCTYB Y4nNy5ewgSREBJqYJR7samEGSTALWEhs3boaaBIHh7BAgET3SyGQMIuAqkRb20GwobwCbhIb Ll5lhlgmJ3Hy2GRWEJtTwF3i9rpDTCCtQkA1z75zT2DkXcDIsIpRNLU0uaA4KT3XSK84Mbe4 NC9dLzk/dxMjJAy/7mBceszqEKMAB6MSD++GKqNwIdbEsuLK3EOMEhzMSiK8c2WNw4V4UxIr q1KL8uOLSnNSiw8xSnOwKInzztz1PkRIID2xJDU7NbUgtQgmy8TBKdXAeJM/QPCqlJTKNY5/ S0RuB4ZMnHSSS95AacuXMw/LNmRzPPdhjWS12nLb0F3JXOrCrBlTH3zz+/XqEkes9vYr/ktW 7MxNXD95InuereCPCIm5h058lnuRFCMaF7puWqaeCfPZN5Y+vG+mTSzbsbw34lGxcl0C26a1 c40jZh3iO8TsJneguTC2UomlOCPRUIu5qDgRAIWHULw/AgAA Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index e26b04fea33b..057c3f0d0e35 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -103,7 +103,7 @@ #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) -static unsigned long exynos3250_cmu_clk_regs[] __initdata = { +static const unsigned long exynos3250_cmu_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -226,7 +226,7 @@ PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; -static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = { FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), @@ -237,7 +237,7 @@ static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), }; -static struct samsung_mux_clock mux_clks[] __initdata = { +static const struct samsung_mux_clock mux_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -326,7 +326,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), }; -static struct samsung_div_clock div_clks[] __initdata = { +static const struct samsung_div_clock div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -429,7 +429,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), }; -static struct samsung_gate_clock gate_clks[] __initdata = { +static const struct samsung_gate_clock gate_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -669,7 +669,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { }; /* APLL & MPLL & BPLL & UPLL */ -static struct samsung_pll_rate_table exynos3250_pll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_pll_rates[] = { PLL_35XX_RATE(1200000000, 400, 4, 1), PLL_35XX_RATE(1100000000, 275, 3, 1), PLL_35XX_RATE(1066000000, 533, 6, 1), @@ -691,7 +691,7 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = { }; /* EPLL */ -static struct samsung_pll_rate_table exynos3250_epll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_epll_rates[] = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), @@ -710,7 +710,7 @@ static struct samsung_pll_rate_table exynos3250_epll_rates[] = { }; /* VPLL */ -static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { +static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = { PLL_36XX_RATE(600000000, 100, 2, 1, 0), PLL_36XX_RATE(533000000, 266, 3, 2, 32768), PLL_36XX_RATE(519230987, 173, 2, 2, 5046), @@ -740,7 +740,7 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { { /* sentinel */ } }; -static struct samsung_pll_clock exynos3250_plls[] __initdata = { +static const struct samsung_pll_clock exynos3250_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, exynos3250_pll_rates), PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", @@ -772,7 +772,7 @@ static void __init exynos3_core_down_clock(void __iomem *reg_base) __raw_writel(0x0, reg_base + PWR_CTRL2); } -static struct samsung_cmu_info cmu_info __initdata = { +static const struct samsung_cmu_info cmu_info __initconst = { .pll_clks = exynos3250_plls, .nr_pll_clks = ARRAY_SIZE(exynos3250_plls), .mux_clks = mux_clks, @@ -848,7 +848,7 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); #define EPLL_CON2 0x111c #define SRC_EPLL 0x1120 -static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { +static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = { BPLL_LOCK, BPLL_CON0, BPLL_CON1, @@ -874,7 +874,7 @@ PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", }; -static struct samsung_mux_clock dmc_mux_clks[] __initdata = { +static const struct samsung_mux_clock dmc_mux_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -893,7 +893,7 @@ static struct samsung_mux_clock dmc_mux_clks[] __initdata = { MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1), }; -static struct samsung_div_clock dmc_div_clks[] __initdata = { +static const struct samsung_div_clock dmc_div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -910,14 +910,14 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = { DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), }; -static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = { +static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates), PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates), }; -static struct samsung_cmu_info dmc_cmu_info __initdata = { +static const struct samsung_cmu_info dmc_cmu_info __initconst = { .pll_clks = exynos3250_dmc_plls, .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls), .mux_clks = dmc_mux_clks, @@ -947,7 +947,7 @@ CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", #define GATE_IP_ISP1 0x804 #define GATE_SCLK_ISP 0x900 -static struct samsung_div_clock isp_div_clks[] __initdata = { +static const struct samsung_div_clock isp_div_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -967,7 +967,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = { DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3), }; -static struct samsung_gate_clock isp_gate_clks[] __initdata = { +static const struct samsung_gate_clock isp_gate_clks[] __initconst = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done @@ -1063,7 +1063,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = { GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), }; -static struct samsung_cmu_info isp_cmu_info __initdata = { +static const struct samsung_cmu_info isp_cmu_info __initconst = { .div_clks = isp_div_clks, .nr_div_clks = ARRAY_SIZE(isp_div_clks), .gate_clks = isp_gate_clks,