From patchwork Mon May 30 14:32:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9141565 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4C17060777 for ; Mon, 30 May 2016 14:34:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F25028185 for ; Mon, 30 May 2016 14:34:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 337262819E; Mon, 30 May 2016 14:34:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC67928185 for ; Mon, 30 May 2016 14:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161524AbcE3Odo (ORCPT ); Mon, 30 May 2016 10:33:44 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48625 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161219AbcE3Odm (ORCPT ); Mon, 30 May 2016 10:33:42 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B79A1612E9; Mon, 30 May 2016 14:33:41 +0000 (UTC) Received: from chewinlnx07.qualcomm.com (unknown [202.46.23.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 78AAC612E7; Mon, 30 May 2016 14:33:34 +0000 (UTC) From: Abhishek Sahu To: andy.gross@linaro.org, david.brown@linaro.org, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk Cc: mturquette@baylibre.com, galak@codeaurora.org, pradeepb@codeaurora.org, mmcclint@codeaurora.org, varada@codeaurora.org, sricharan@codeaurora.org, architt@codeaurora.org, ntelkar@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abhishek Sahu Subject: [PATCH 4/5] clk: qcom: ipq4019: Added the cpu clock frequency change notifier Date: Mon, 30 May 2016 20:02:37 +0530 Message-Id: <1464618758-20965-5-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464618758-20965-1-git-send-email-absahu@codeaurora.org> References: <1464618758-20965-1-git-send-email-absahu@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current IPQ4019 clock driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so the APPS clock need to be switched for stable clock duringthe change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 when it gets for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/gcc-ipq4019.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c index 263577c..69a8250 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c @@ -1455,9 +1455,27 @@ static const struct of_device_id gcc_ipq4019_match_table[] = { }; MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table); +int cpu_clk_notifier_fn(struct notifier_block *nb, + unsigned long action, void *data) +{ + int err = 0; + + if (action == PRE_RATE_CHANGE) { + err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw, + P_FEPLL500); + } + + return notifier_from_errno(err); +} + +struct notifier_block cpu_clk_notifier = { + .notifier_call = cpu_clk_notifier_fn, +}; + static int gcc_ipq4019_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + int err; clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000); clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000); @@ -1469,7 +1487,13 @@ static int gcc_ipq4019_probe(struct platform_device *pdev) clk_register_fixed_rate(dev, "ddrpllsdcc", "xo", 0, 193000000); clk_register_fixed_rate(dev, "pcnoc_clk_src", "xo", 0, 100000000); - return qcom_cc_probe(pdev, &gcc_ipq4019_desc); + err = qcom_cc_probe(pdev, &gcc_ipq4019_desc); + + if (!err) + clk_notifier_register(apps_clk_src.clkr.hw.clk, + &cpu_clk_notifier); + + return err; } static struct platform_driver gcc_ipq4019_driver = {