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dkim=none (message not signed) header.d=none; nxp.com; dmarc=none action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD039.mail.protection.outlook.com (10.58.52.243) with Microsoft SMTP Server (TLS) id 15.1.497.8 via Frontend Transport; Wed, 8 Jun 2016 14:39:33 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id u58EdPaO005456; Wed, 8 Jun 2016 07:39:29 -0700 From: Dong Aisheng To: CC: , , , , , , Subject: [PATCH 02/11] clk: imx: correct AV PLL rate formula Date: Wed, 8 Jun 2016 22:33:31 +0800 Message-ID: <1465396420-27064-2-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465396420-27064-1-git-send-email-aisheng.dong@nxp.com> References: <1465396420-27064-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131098703737736868; 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BY1PR03MB1452; 5:mGygkKSiZEsVdorojjVetsmd39eNgIEOMYIqOURoteLBiQ0dHf38xQene/OO4DEs6azdo1GGv+gHzfAWj7u+COx1JqxZre9oUAlHTVrv3EJe7LDY2nPslxskJGGND29BRvFGk46J9JQlvdB4q6uRjtISLx4MhYQ2g3fJzs0oMiQ=; 24:YtbZn9stAneOerFTN31dcrELCLG5HiixDANqW+/tBNo6r8w8n63BjfqPBUFtcfTAsEKosa/jeF2NbsO6LMfnBsUsp745jETUBcbQK7E5ioI=; 7:LAVIpeaok9Da3rzkK6A6TC08hZOl1lL015bNauPOpAHKpWpzfmiR0NAU/E9tdLBV7ufFn/VWg8pIwbNZ7CmOGzepxqmMsFobM7QdeQmoolMHG/GIeKlZauGtxb9/7qYffg2inlbxIGX2KSsTyGQrsw0qszeDdH2OIeyd2N8jQYMZLGpgrDgZLQnoFr+Vsh9X/R8D9pNHkal8GN1EGgs1/8AN19tJuFEDgKXKe/Txnbs= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2016 14:39:33.2120 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1452 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Anson Huang The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-pllv3.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 44d294a336f0..eea2b1b3791e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -218,8 +218,12 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); u32 div = readl_relaxed(pll->base) & pll->div_mask; + u64 temp64 = (u64)parent_rate; - return (parent_rate * div) + ((parent_rate / mfd) * mfn); + temp64 *= mfn; + do_div(temp64, mfd); + + return (parent_rate * div) + (u32)temp64; } static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, @@ -243,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, do_div(temp64, parent_rate); mfn = temp64; - return parent_rate * div + parent_rate / mfd * mfn; + return parent_rate * div + parent_rate * mfn / mfd; } static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,