From patchwork Fri Jun 10 00:32:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Turquette X-Patchwork-Id: 9168669 X-Patchwork-Delegate: mturquette@baylibre.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 07390604DB for ; Fri, 10 Jun 2016 00:33:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE6F028047 for ; Fri, 10 Jun 2016 00:33:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E31EB28368; Fri, 10 Jun 2016 00:33:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8111C28047 for ; Fri, 10 Jun 2016 00:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751119AbcFJAdB (ORCPT ); Thu, 9 Jun 2016 20:33:01 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:33643 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751056AbcFJAdA (ORCPT ); Thu, 9 Jun 2016 20:33:00 -0400 Received: by mail-pa0-f47.google.com with SMTP id ec8so18003553pac.0 for ; Thu, 09 Jun 2016 17:33:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=htgnV/UNAkBrUQMGZxVSDARTHmrcXUsaC5X28XchyyE=; b=lQF2bspGwIhYQK+M3aWCW7EW7eR7A9h0nkMOY4Nx2d+M1vNPuCQ7sKqrYcLjzx3Vwq Ec7rZZbsiCIJr5SV073CDWjHWbn/3m0mcF6/h5VcZZKslOYRUYOZ8z6AugimcGYPO9hl /IYLPo8PJHB+JbRPBVVPw9A28IUCFv9hPIQQ7VwqVeh61LQTM7R5kRqVPTfYWtLOdQzU 69YjRydD07BxJT9nUZBkBVWI2JStg0WJUvkTDEzGFY+ZXhzXgKU99Ow5mhvKCLsebKSV Ak1KTy+2WzVqdx/sgnluOuRsRRb8vbWTQHobslbMlozCK8YcCCGNdK+9OmkuxOxAdjJ5 2P1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=htgnV/UNAkBrUQMGZxVSDARTHmrcXUsaC5X28XchyyE=; b=QdKwrX0OMZF9v+HHcYa+wN1Gja8QhYUBZFkjJO9ajbpwzsaQND7r3w5IManP6l9FUQ U2j0CpSUYeh+te5yrha+BH/lXjmGqdRoQAJhZHHOVBD/0rYPF0Xc9nO8tszfxp4yHYH2 PuMsOFq4U/fhtBL//1tV6DxoVmqiw85eENojvUiRt/YoY3iX7xXhgXHJsUObbJAArzld GWLM8G4dsRwZGr9U5fieoUVVOasMMydMoS+Jsq6HEC/mPWG9arDnSA3rjgDl0qw7QOjd 7VEuI5wqpKekBPDeNc29Z+gwh26JICvUfSgIjDywnXuM9ohOfIIMV1BX4b2AdRtUUr6G 2WsQ== X-Gm-Message-State: ALyK8tI/MgP+BWeceTxVPppVQ1Nv8L5T7gvUk5sIr4G0qxZ3FoFq653ZVV96hQRhXdQWexPC X-Received: by 10.66.186.70 with SMTP id fi6mr15266976pac.3.1465518779916; Thu, 09 Jun 2016 17:32:59 -0700 (PDT) Received: from localhost (cpe-172-248-200-249.socal.res.rr.com. [172.248.200.249]) by smtp.gmail.com with ESMTPSA id ih15sm12682943pab.38.2016.06.09.17.32.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jun 2016 17:32:59 -0700 (PDT) From: Michael Turquette To: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org, khilman@baylibre.com, carlo@endlessm.com, victor.wan@amlogic.com, jerry.cao@amlogic.com, xing.xu@amlogic.com Subject: [PATCH 3/7] clk: meson: fractional pll support Date: Thu, 9 Jun 2016 17:32:50 -0700 Message-Id: <1465518774-26924-4-git-send-email-mturquette@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1465518774-26924-1-git-send-email-mturquette@baylibre.com> References: <1465518774-26924-1-git-send-email-mturquette@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Michael Turquette --- drivers/clk/meson/clk-pll.c | 32 ++++++++++++++++++++++++++++++-- drivers/clk/meson/clkc.h | 15 +++++++++++++++ 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 60c6b94..4adc1e8 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -53,7 +53,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, struct parm *p; unsigned long parent_rate_mhz = parent_rate / 1000000; unsigned long rate_mhz; - u16 n, m, od; + u16 n, m, frac = 0, od, od2 = 0; u32 reg; p = &pll->n; @@ -68,7 +68,21 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, reg = readl(pll->base + p->reg_off); od = PARM_GET(p->width, p->shift, reg); - rate_mhz = (parent_rate_mhz * m / n) >> od; + p = &pll->od2; + if (p->width) { + reg = readl(pll->base + p->reg_off); + od2 = PARM_GET(p->width, p->shift, reg); + } + + p = &pll->frac; + if (p->width) { + reg = readl(pll->base + p->reg_off); + frac = PARM_GET(p->width, p->shift, reg); + rate_mhz = (parent_rate_mhz * m + \ + (parent_rate_mhz * frac >> 12)) * 2 / n; + rate_mhz = rate_mhz >> od >> od2; + } else + rate_mhz = (parent_rate_mhz * m / n) >> od >> od2; return rate_mhz * 1000000; } @@ -155,6 +169,20 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, reg = PARM_SET(p->width, p->shift, reg, rate_set->od); writel(reg, pll->base + p->reg_off); + p = &pll->od2; + if (p->width) { + reg = readl(pll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, rate_set->od2); + writel(reg, pll->base + p->reg_off); + } + + p = &pll->frac; + if (p->width) { + reg = readl(pll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, rate_set->frac); + writel(reg, pll->base + p->reg_off); + } + p = &pll->n; ret = meson_clk_pll_wait_lock(pll, p); if (ret) { diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 73f0146..53326c3 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -40,7 +40,10 @@ struct pll_rate_table { u16 m; u16 n; u16 od; + u16 od2; + u16 frac; }; + #define PLL_RATE(_r, _m, _n, _od) \ { \ .rate = (_r), \ @@ -49,12 +52,24 @@ struct pll_rate_table { .od = (_od), \ } \ +#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ + { \ + .rate = (_r), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ + .od2 = (_od2), \ + .frac = (_frac), \ + } \ + struct meson_clk_pll { struct clk_hw hw; void __iomem *base; struct parm m; struct parm n; + struct parm frac; struct parm od; + struct parm od2; const struct pll_rate_table *rate_table; unsigned int rate_count; spinlock_t *lock;