From patchwork Fri Jun 10 04:56:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 9168809 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ABCAC604DB for ; Fri, 10 Jun 2016 04:57:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A1C4B28325 for ; Fri, 10 Jun 2016 04:57:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 967D22833F; Fri, 10 Jun 2016 04:57:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0106428325 for ; Fri, 10 Jun 2016 04:57:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752320AbcFJE5I (ORCPT ); Fri, 10 Jun 2016 00:57:08 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:54863 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752240AbcFJE5C (ORCPT ); Fri, 10 Jun 2016 00:57:02 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O8J008F7HQJ5I30@mailout4.samsung.com>; Fri, 10 Jun 2016 13:56:43 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.112]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 7F.C5.04903.B884A575; Fri, 10 Jun 2016 13:56:43 +0900 (KST) X-AuditID: cbfee690-f79056d000001327-75-575a488b7e9f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id E0.A2.06657.B884A575; Fri, 10 Jun 2016 13:56:43 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O8J00G42HQIA070@mmp2.samsung.com>; Fri, 10 Jun 2016 13:56:43 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, jh80.chung@samsung.com, jonghwa3.lee@samsung.com, beomho.seo@samsung.com, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chanwoo Choi Subject: [PATCH 3/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device Date: Fri, 10 Jun 2016 13:56:32 +0900 Message-id: <1465534592-18860-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1465534592-18860-1-git-send-email-cw00.choi@samsung.com> References: <1465534592-18860-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42JZI2JSoNvtERVusOCBsMXpT9vYLa5/ec5q ceNXG6tF59knzBavXxha9D9+zWyx6fE1VouPPfdYLS7vmsNmMeP8PiaLi6dcLQ6/aWe1+HGm m8Vi1a4/jA58Hu9vtLJ7XO7rZfLYOesuu8emVZ1sHpuX1Hv0bVnF6PF5k1wAexSXTUpqTmZZ apG+XQJXxo4bD9kLLkhV7PzZxNzA+F6si5GTQ0LARKL5wjUWCFtM4sK99WxdjFwcQgIrGCWa rz1j7GLkACv62uMMEZ/FKPH82jEWCOcLo8T+T13MIN1sAloS+1/cYANpEBEwlLh5SAmkhlng GpPEylnvWEFqhAWiJG79mswOYrMIqErseLkUbDOvgKvE474v7BBXyEl82PMIzOYUcJNY9PcX G4gtBFTzo+EL2HUSAvfYJQ6928YGMUhA4tvkQywQl8pKbDrADDFHUuLgihssExiFFzAyrGIU TS1ILihOSi8y0StOzC0uzUvXS87P3cQIjJ3T/55N2MF474D1IUYBDkYlHl6DR5HhQqyJZcWV uYcYTYE2TGSWEk3OB0ZoXkm8obGZkYWpiamxkbmlmZI472upn8FCAumJJanZqakFqUXxRaU5 qcWHGJk4OKUaGBle3RVg7vD4vTzJ5FBjKOeE5RO76uw4L4fzV27RuDR1zlH1BWIbLygprvgt 3PDV5OL3NzvMeS2//vkgu/Dugkcb9T/8/rXeeHPIv/uxjzpchI9v/VjhNNPminZ7+MejP9yF r+5n23G0Y9Eqq4Ll/ze8ZVPLZNp011mvkbXFUSmuiIfNsnjKy+VKLMUZiYZazEXFiQAQv9cm mAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEIsWRmVeSWpSXmKPExsVy+t9jQd1uj6hwg5UzeS1Of9rGbnH9y3NW ixu/2lgtOs8+YbZ4/cLQov/xa2aLTY+vsVp87LnHanF51xw2ixnn9zFZXDzlanH4TTurxY8z 3SwWq3b9YXTg83h/o5Xd43JfL5PHzll32T02repk89i8pN6jb8sqRo/Pm+QC2KMaGG0yUhNT UosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVcfAJ03TJzgC5WUihLzCkFCgUk Fhcr6dthmhAa4qZrAdMYoesbEgTXY2SABhLWMGbsuPGQveCCVMXOn03MDYzvxboYOTgkBEwk vvY4dzFyApliEhfurWfrYuTiEBKYxSjx/NoxFgjnC6PE/k9dzCBVbAJaEvtf3GADaRYRMJS4 eUgJpIZZ4BqTxMpZ71hBaoQFoiRu/ZrMDmKzCKhK7Hi5lAXE5hVwlXjc94UdYpucxIc9j8Bs TgE3iUV/f7GB2EJANT8avrBNYORdwMiwilEitSC5oDgpPdcwL7Vcrzgxt7g0L10vOT93EyM4 Pp9J7WA8uMv9EKMAB6MSD2/ErshwIdbEsuLK3EOMEhzMSiK8X5yiwoV4UxIrq1KL8uOLSnNS iw8xmgIdNpFZSjQ5H5g68kriDY1NzIwsjcwNLYyMzZXEeR//XxcmJJCeWJKanZpakFoE08fE wSnVwHisK7W3+oVIa7G8+94wKfNXgZe/fduW4LZHon7WDIa9XrZfy1/bbst23PtP84FKIifz n+e6mxOsLicnthtq22xj9ZKSvudgYburfUnBmdla6wv/rMgQ8u354pJwymVeu9x69gdeb5vZ 2hhcdqTrRfP5yNye0eszJbt3z/OidStOn+bOOZ26V4mlOCPRUIu5qDgRAIW0rNXlAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jaehoon Chung This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need the on state and the 'pcie' gate clock. Signed-off-by: Jaehoon Chung Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 11 ++++++----- include/dt-bindings/clock/exynos5433.h | 3 ++- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 852ac6a7607e..e3cc9359fb20 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -639,7 +639,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { /* ENABLE_SCLK_TOP_FSYS */ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", - ENABLE_SCLK_TOP_FSYS, 7, 0, 0), + ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", @@ -2146,7 +2146,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = { GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", - ENABLE_ACLK_FSYS1, 24, 0, 0), + ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 22, CLK_IGNORE_UNUSED, 0), @@ -2193,13 +2193,13 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = { /* ENABLE_PCLK_FSYS */ GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 17, 0, 0), + ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 14, 0, 0), + ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", - ENABLE_PCLK_FSYS, 13, 0, 0), + ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", @@ -2278,6 +2278,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = { ENABLE_SCLK_FSYS, 0, 0, 0), /* ENABLE_IP_FSYS0 */ + GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 8e024fea26e7..4fa6bb2136e3 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -622,8 +622,9 @@ #define CLK_SCLK_UFSUNIPRO 112 #define CLK_SCLK_USBHOST30 113 #define CLK_SCLK_USBDRD30 114 +#define CLK_PCIE 115 -#define FSYS_NR_CLK 115 +#define FSYS_NR_CLK 116 /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1