From patchwork Tue Jun 21 04:59:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 9189465 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A36AA6089F for ; Tue, 21 Jun 2016 05:02:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92AAE27F94 for ; Tue, 21 Jun 2016 05:02:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 875AC27F9E; Tue, 21 Jun 2016 05:02:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 047E627F99 for ; Tue, 21 Jun 2016 05:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752034AbcFUFCg (ORCPT ); Tue, 21 Jun 2016 01:02:36 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:41138 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750754AbcFUFCc (ORCPT ); Tue, 21 Jun 2016 01:02:32 -0400 Received: from zhengxing?rock-chips.com (unknown [192.168.167.236]) by regular1.263xmail.com (Postfix) with SMTP id 60D80623F; Tue, 21 Jun 2016 12:59:57 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 7A32034C8; Tue, 21 Jun 2016 12:59:55 +0800 (CST) X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: zhengxing@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 14226VJRLJ9; Tue, 21 Jun 2016 12:59:57 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, zhengxing@rock-chips.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ykk@rock-chips.com, jeffy.chen@rock-chips.com, wxt@rock-chips.com Subject: [PATCH 5/5] clk: rockchip: rk3228: export related MAC clocks Date: Tue, 21 Jun 2016 12:59:47 +0800 Message-Id: <1466485187-27081-1-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1466484811-26923-1-git-send-email-zhengxing@rock-chips.com> References: <1466484811-26923-1-git-send-email-zhengxing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3228.c | 22 +++++++++++----------- include/dt-bindings/clock/rk3228-cru.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 980d0da..db6e5a9 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -499,25 +499,25 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), - COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, + COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0, RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), - MUX(0, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0, + MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0, RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), - MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, + MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), - GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, + GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS), - GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, + GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), - GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, + GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS), - GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, + GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), - COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, + COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0, RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), - COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, + COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0, RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), @@ -551,7 +551,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { /* PD_PERI */ GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), - GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), @@ -567,7 +567,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), - GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), /* PD_GPU */ diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index c992f3e..b27e2b1 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -52,6 +52,15 @@ #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 /* dclk gates */ #define DCLK_VOP 190 @@ -61,6 +70,7 @@ #define ACLK_DMAC 194 #define ACLK_PERI 210 #define ACLK_VOP 211 +#define ACLK_GMAC 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -82,6 +92,7 @@ #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 /* hclk gates */ #define HCLK_I2S0_8CH 442