From patchwork Tue Jun 28 10:31:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9202549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 785EA60757 for ; Tue, 28 Jun 2016 10:31:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62B9328618 for ; Tue, 28 Jun 2016 10:31:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5755B28602; Tue, 28 Jun 2016 10:31:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF9812860F for ; Tue, 28 Jun 2016 10:31:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752121AbcF1Kbz (ORCPT ); Tue, 28 Jun 2016 06:31:55 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:34902 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752102AbcF1Kby (ORCPT ); Tue, 28 Jun 2016 06:31:54 -0400 Received: by mail-pf0-f179.google.com with SMTP id c2so5621870pfa.2 for ; Tue, 28 Jun 2016 03:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=62NBWjH7+92KKM7UO2Gfx1Bgx+w4WTsYBoMlzaRRk9k=; b=KF4MxgPJgGWkBwD+1/BlriWocq2Zku+6WCS16vF3rkQJCvhDHPv8gAI1/YeWH1/Tap PY2++dq6GPfnf3GM5NSq3ZdiqbcOqVuowg1iOnsB/wBtwfnjgVHwQRhjGta8y74zcjVQ 6QeOeOgavvUiqQFeZpz+sVLEHFcoouHVaF/oY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=62NBWjH7+92KKM7UO2Gfx1Bgx+w4WTsYBoMlzaRRk9k=; b=PEb2W5IEKHItD3oBn9LTqsFZhx4ptmOs9JuDrTZ5wNsC1NxTh6izzMzon4lNVPBN4R rZzwyeUGEku/8q/p7il9DQyyCY4vBhxyL78PoQHEvHZZ45YnmmUSSlXgdNb7sZzLNt6c 8JzQYfbdZBEaPT5aY13lDYTStkjuLCtD8POo5KQq4Sgg+Fa+PloBenYY4c535NjFUOeb 7h+hMNX/B2ygjkdWRbsxFwUTjijgmKslniBhWvA7RQQnWgPJvEGL4KSAi/PBBZMN78D6 NAp8MVhiRnYiPWr3xkZum8HC6mkboWoeEhXIHcC0wQV7Bpk9o9JraFimwTuMfCrcxVMC qjaw== X-Gm-Message-State: ALyK8tIUFZKYPnJSSFyqcJ3UKlU2taO9nqGRIO69XwpKg4d/sQALO6OrWvBgau4rCocFS3mA X-Received: by 10.98.69.199 with SMTP id n68mr499931pfi.160.1467109913687; Tue, 28 Jun 2016 03:31:53 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.9]) by smtp.gmail.com with ESMTPSA id d8sm5801433pfg.72.2016.06.28.03.31.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Jun 2016 03:31:53 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, jorge.ramirez-ortiz@linaro.org, xinliang.liu@linaro.org, guodong.xu@linaro.org, john.stultz@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/2] clk: hi6220: Change syspll and media_syspll clk to 1.19GHz Date: Tue, 28 Jun 2016 18:31:41 +0800 Message-Id: <1467109902-17625-1-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Xinliang Liu In the bootloader of HiKey/96boards, syspll and media_syspll clk was initialized to 1.19GHz. So, here changes it in kernel accordingly. 1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI (74.25MHz required by standards). Closer pixel clock means better compatibility to HDMI monitors. Signed-off-by: Guodong Xu Signed-off-by: Xinliang Liu --- drivers/clk/hisilicon/clk-hi6220.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index f02cb41..a36ffcb 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -34,8 +34,8 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, }, { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,}, { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,}, - { HI6220_PLL_SYS, "syspll", NULL, 0, 1200000000,}, - { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1200000000,}, + { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,}, + { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,}, { HI6220_DDR_SRC, "ddr_sel_src", NULL, 0, 1200000000,}, { HI6220_PLL_MEDIA, "media_pll", NULL, 0, 1440000000,}, { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,},