From patchwork Tue Jun 28 10:31:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9202553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8ABF060757 for ; Tue, 28 Jun 2016 10:32:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BE7C285C6 for ; Tue, 28 Jun 2016 10:32:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F808285E6; Tue, 28 Jun 2016 10:32:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 50B43285C6 for ; Tue, 28 Jun 2016 10:32:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752115AbcF1KcA (ORCPT ); Tue, 28 Jun 2016 06:32:00 -0400 Received: from mail-pf0-f177.google.com ([209.85.192.177]:32920 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752263AbcF1Kb6 (ORCPT ); Tue, 28 Jun 2016 06:31:58 -0400 Received: by mail-pf0-f177.google.com with SMTP id i123so5654645pfg.0 for ; Tue, 28 Jun 2016 03:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=svoVkYTlK/84c2mNqVgdqLq/mrJG8eZrLUry9JTIIhE=; b=ZsEw0tNp1HeWLYWNj7fmQ87BthcXsg0FIGUbcGG70VwPlaR3cR39PwqaK7m2xSgmRS 0jP4VWJsD7410I4W6A8mDRiAm0fQR41zTj4cF3TH+StYctKkxibuuVIYRrBxBWt8nXOG 2yHvG3ug9mlX+4F8K5aRLsGnJbleQ7IiK+QKw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=svoVkYTlK/84c2mNqVgdqLq/mrJG8eZrLUry9JTIIhE=; b=EFmj/GIM+AGhLZm0H3vi20RX/5gHJGjSwK90oVPPzNsLPRJeQNbIxod6jqfSU7gdZM 2x6Slfq8aM9inuLxL7lbSYk3Hw7n5ITVtR1M4VIXiuQElj/NbFBYpZoKjlS5r7D6Lc02 cJQZPMMBhNEiVtkFiO+EN8TKeYQk3rF7OIv0spTdTUVBN1JhBGF74QtZc8uqr7qzK06A dhTm1imq6ZZtoOIsSJ1APek9qKd2D8p7P6FwefmPaobTulmVsbIMPZJKuAU349S4USpp +N5neXxacjKNvZTnlRklECFRffmV6CmRjJcpwrxS0SQGTm+XIWOEIUB5o9S2HlcNB0oE 4JZA== X-Gm-Message-State: ALyK8tKMuyPKXBN57p5FuVRdQjOKGoVXikvweabBWfmcKxwJW9YPxU16J+rH5g6OBrtQd9nk X-Received: by 10.98.208.197 with SMTP id p188mr506632pfg.152.1467109918226; Tue, 28 Jun 2016 03:31:58 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.9]) by smtp.gmail.com with ESMTPSA id d8sm5801433pfg.72.2016.06.28.03.31.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Jun 2016 03:31:57 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, jorge.ramirez-ortiz@linaro.org, xinliang.liu@linaro.org, guodong.xu@linaro.org, john.stultz@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: hi6220: initialize UART1 clock to 150MHz Date: Tue, 28 Jun 2016 18:31:42 +0800 Message-Id: <1467109902-17625-2-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467109902-17625-1-git-send-email-guodong.xu@linaro.org> References: <1467109902-17625-1-git-send-email-guodong.xu@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jorge Ramirez-Ortiz Early at boot, during the sys_clk initialization, make sure UART1 uses the higher frequency clock. This enables support for higher baud rates (up to 3Mbps) required to support faster bluetooth transfers. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi6220.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index a36ffcb..55bd9bb 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -70,10 +71,10 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, }; +static struct hisi_clock_data *clk_data_ao; + static void __init hi6220_clk_ao_init(struct device_node *np) { - struct hisi_clock_data *clk_data_ao; - clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; @@ -192,6 +193,13 @@ static void __init hi6220_clk_sys_init(struct device_node *np) hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); + + if (!clk_data_ao) + return; + + /* enable high speed clock on UART1 mux */ + clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], + clk_data_ao->clk_data.clks[HI6220_150M]); } CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);