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Thu, 30 Jun 2016 16:15:15 +0900 (KST) From: Andi Shyti To: Chanwoo Choi Cc: Jaehoon Chung , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andi Shyti , Andi Shyti Subject: [PATCH v3 2/2] clk: exynos5433: enable sclk_ioclk for SPI3 Date: Thu, 30 Jun 2016 16:15:11 +0900 Message-id: <1467270911-10971-3-git-send-email-andi.shyti@samsung.com> X-Mailer: git-send-email 2.8.1 In-reply-to: <1467270911-10971-1-git-send-email-andi.shyti@samsung.com> References: <1467270911-10971-1-git-send-email-andi.shyti@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42JZI2JSqMtyvCTc4M9HLovtR56xWiz+8ZzJ 4vqX56wWN361sVq8fmFo0f/4NbPFpsfXWC0+9txjtbi8aw6bxYzz+5gsLp5ytTj8pp3V4seZ bhaLVbv+MDrweby/0crucbmvl8nj+pJPzB47Z91l99i0qpPNY/OSeo++LasYPT5vkgvgiOKy SUnNySxLLdK3S+DKmHZgNnPBdp6KN1+PsjYw3ubqYuTkkBAwkXh7ZDILhC0mceHeerYuRi4O IYEVjBJrTx9jgyla9mYhM0RiFqPEsU2/GSGcj4wSJ7tugbWzCWhKNN3+AdYhIqAhMfPvFUYQ m1ngE7PExz6fLkYODmEBZ4kpL6tAwiwCqhLtH3rBWnkF3CTO7tjIDrFMTuLy9AdgYzgF3CX+ z/4EZgsB1ZzZ0MIKsldC4BG7xIEFU9kgBglIfJt8iAVkvoSArMSmA8wQcyQlDq64wTKBUXgB I8MqRtHUguSC4qT0ImO94sTc4tK8dL3k/NxNjMAoOv3vWf8OxrsHrA8xCnAwKvHwTvAsCRdi TSwrrsw9xGgKtGEis5Rocj4wVvNK4g2NzYwsTE1MjY3MLc2UxHkXSv0MFhJITyxJzU5NLUgt ii8qzUktPsTIxMEp1cC4ehoTO+9t7/dLn1TaV1zr87N6f4dvpkfm1UqL5dvbbhxs3P1b4abw r4cscffeOPKoPF41224393/HllXqOes+8Ty4baP1/OAz84P2Bg8EmNaL/L2WY3JcNV9+ud+i /RMfMLyasav6HbvpVtc3fto2TaGejVwSRaw3fmi7MCr6NxfOVVYP7VRWYinOSDTUYi4qTgQA PlKrf50CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsVy+t9jQV2W4yXhBp3XWS22H3nGarH4x3Mm i+tfnrNa3PjVxmrx+oWhRf/j18wWmx5fY7X42HOP1eLyrjlsFjPO72OyuHjK1eLwm3ZWix9n ulksVu36w+jA5/H+Riu7x+W+XiaP60s+MXvsnHWX3WPTqk42j81L6j36tqxi9Pi8SS6AI6qB 0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6GwlhbLE nFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8a0A7OZC7bzVLz5epS1gfE2Vxcj J4eEgInEsjcLmSFsMYkL99azdTFycQgJzGKUOLbpNyOE85FR4mTXLRaQKjYBTYmm2z/YQGwR AQ2JmX+vMILYzAKfmCU+9vl0MXJwCAs4S0x5WQUSZhFQlWj/0AvWyivgJnF2x0Z2iGVyEpen PwAbwyngLvF/9icwWwio5syGFtYJjLwLGBlWMUqkFiQXFCel5xrlpZbrFSfmFpfmpesl5+du YgRH6jPpHYyHd7kfYhTgYFTi4T2wryRciDWxrLgy9xCjBAezkgjvxoNAId6UxMqq1KL8+KLS nNTiQ4ymQIdNZJYSTc4HJpG8knhDYxMzI0sjc0MLI2NzJXHex//XhQkJpCeWpGanphakFsH0 MXFwSjUwdurutsrUNHtTnvohpU9s8XtJt+qp+Xu+1TX+qPjz+7R80vXk0K1bXpT7L+bMbrWQ 39bmtNQreMWi0zxKe/myVKKulvdsncNpEfFV5sl0s9dnNf9NamRpVp139EDAmpymSX675Qvy pDbcN9vhd+QJ49RFG2QbI7+8aAn8Xb/kx7K8KC+b738llFiKMxINtZiLihMB+hmQtuoCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP enable SPI3 critical clocks by using the CLK_IS_CRITICAL flag. There is no device which is supposed to enable this clock when needed, therefore, the only way to use the SPI bus is to enable it in boot time. Suggested-by: Tomasz Figa Signed-off-by: Andi Shyti Signed-off-by: Jaehoon Chung Reviewed-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 1f7c4951..e769c80 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -1648,11 +1648,12 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", - ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 20, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 19, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, - 18, CLK_SET_RATE_PARENT, 0), + 18, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 17, 0, 0), GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,