From patchwork Tue Jul 19 13:36:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mirza Krak X-Patchwork-Id: 9237425 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CCCFC602F0 for ; Tue, 19 Jul 2016 13:36:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBF271FF27 for ; Tue, 19 Jul 2016 13:36:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A647B26E81; Tue, 19 Jul 2016 13:36:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40B6B1FF27 for ; Tue, 19 Jul 2016 13:36:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753862AbcGSNg6 (ORCPT ); Tue, 19 Jul 2016 09:36:58 -0400 Received: from mail-lf0-f66.google.com ([209.85.215.66]:34889 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753722AbcGSNgz (ORCPT ); Tue, 19 Jul 2016 09:36:55 -0400 Received: by mail-lf0-f66.google.com with SMTP id l89so1319353lfi.2; Tue, 19 Jul 2016 06:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SRC0BMXV1jf4KcfJbyVB3M0XFwckXzDUsJQDmZ4iH60=; b=eEkOJLoEEZSFFpDN6vKskZU+x3XHnQe/ONkSAG/lpKVdJwPZ8VljUfqr1lU0v7klSY qn9cT8pMW3me6/wcRJznaEzdVolRkj3BKuX95svJilhPY6lVl15X16hk/VQIQPebiBPA Rj2P2LrhT8mLOoTA4B+TRFH0a14ApAwdUXGxk9elLFgIqmrPCu8ud7hSiCv+Ge0fJUha tb23atULIBhz1mbe6tgpBm1ujobBv12DdIM2PCYsCguzM6T/XvXcw0Y+G2vc6vjq5RAa 2IZKFVC5GnePxSha/6t4tfLm0NTVRefSRRfE3eWl7JaKdavSSV2bChCv6JCF422gt4Wu vDmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SRC0BMXV1jf4KcfJbyVB3M0XFwckXzDUsJQDmZ4iH60=; b=TlzQA1bp3YZUDYWOKQKj2DVFuUd4IlY174NSn2PHhd9YQfVk138HZIvmcj0EcktxL+ 8J4dizOMLduOKNIQI8irhbrgSVV7Q1iUfoKFoI3BdUasJYwlDjQ62NCGTH/e6TstGHe6 ohAhS36LsOAcNFmDkVZci+EzEemN5XyoYXPNSFo4fbITYWraPQO403MylwY2mUr9STK2 o1m0ijerd1ZpRYs5udIFpm23C2a+Pe0WxTv0vureYu3M7g1f7+5L47TMu2cvRi/6Q93j aBKHtFrmmqDkA8o1WfDlmZ6VgRV+E06arGsJhYAy7SLyIE9EK2cm69sCwiyqKvZ7dd9K iY4w== X-Gm-Message-State: ALyK8tJhh6H3/cgZan66N6VoadQWyiWyaI36xPOuCMjviflvhs/VZ3zWWiTBekJbbTU3Ag== X-Received: by 10.46.5.196 with SMTP id 187mr15003947ljf.13.1468935412937; Tue, 19 Jul 2016 06:36:52 -0700 (PDT) Received: from mirza-hm.lan ([80.252.212.150]) by smtp.gmail.com with ESMTPSA id l129sm3395942lfl.37.2016.07.19.06.36.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Jul 2016 06:36:52 -0700 (PDT) From: Mirza Krak X-Google-Original-From: Mirza Krak < mirza.krak@gmail.com > To: swarren@wwwdotorg.org, thierry.reding@gmail.com, gnurou@gmail.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@armlinux.org.uk, Mirza Krak Subject: [RFC 3/6] dt/bindings: Add bindings for Tegra20/30 NOR bus driver Date: Tue, 19 Jul 2016 15:36:34 +0200 Message-Id: <1468935397-11926-4-git-send-email-mirza.krak@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1468935397-11926-1-git-send-email-mirza.krak@gmail.com> References: <1468935397-11926-1-git-send-email-mirza.krak@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mirza Krak Document the devicetree bindings for NOR bus driver found on Tegra20 and Tegra30 SOCs Signed-off-by: Mirza Krak --- .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt new file mode 100644 index 0000000..9ee4a66 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt @@ -0,0 +1,73 @@ +Device tree bindings for NVIDIA Tegra20/30 NOR Bus + +The NOR controller supports a number of memory types, including synchronous NOR, +asynchronous NOR, and other flash memories with similar interfaces, such as +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs, +CAN chips, Wi-Fi chips etc. + +The actual devices are instantiated from the child nodes of a NOR node. + +Required properties: + + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor" + - reg: Should contain NOR controller registers location and length. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names : Must include the following entries: + - nor + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - ranges: Must be set up to reflect the memory layout with four integer + values for each chip-select line in use. + - nvidia,config: This property represents the SNOR_CONFIG_0 register. + +Note that the NOR controller does not have any internal chip-select address +decoding and if you want to access multiple devices external chip-select +decoding must be provided. + +Optional properties: + + - nvidia,cs-timing: The timing array represents the SNOR_TIMING0_0 and + SNOR_TIMING1_0 registers for the NOR controller. If unset reset-values will + be used. See reference documentation for detailed description of the timing + registers. + +Example with two SJA1000 CAN controllers connected to the NOR bus: + + nor@70009000 { + status = "okay"; + compatible = "nvidia,tegra20-nor", "nvidia,tegra30-nor"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&tegra_car TEGRA30_CLK_NOR>; + resets = < &tegra_car 42>; + reset-names = "nor"; + ranges = < + 0 0 0x48000000 0x00000100 + 1 0 0x48040000 0x00000100 + >; + + can@0,0 { + compatible = "nxp,sja1000"; + reg = <0 0 0x100>; + interrupt-parent = <&gpio>; + interrupts = ; + nxp,external-clock-frequency = <24000000>; + nxp,tx-output-config = <0x16>; + nxp,clock-out-frequency = <24000000>; + reg-io-width = <2>; + }; + + + can@1,0 { + compatible = "nxp,sja1000"; + reg = <1 0 0x100>; + interrupt-parent = <&gpio>; + interrupts = ; + nxp,external-clock-frequency = <24000000>; + nxp,tx-output-config = <0x16>; + reg-io-width = <2>; + };