From patchwork Fri Aug 12 10:51:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keguang Zhang X-Patchwork-Id: 9276721 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C89660752 for ; Fri, 12 Aug 2016 10:52:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D45B28977 for ; Fri, 12 Aug 2016 10:52:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21D1228979; Fri, 12 Aug 2016 10:52:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB4BB28977 for ; Fri, 12 Aug 2016 10:52:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752630AbcHLKwR (ORCPT ); Fri, 12 Aug 2016 06:52:17 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33558 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752432AbcHLKwP (ORCPT ); Fri, 12 Aug 2016 06:52:15 -0400 Received: by mail-pf0-f195.google.com with SMTP id i6so1383369pfe.0; Fri, 12 Aug 2016 03:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mx1x7WXdWx1OmGiQa8j/Ocnd1yGzb9TNnARrKEjT+x4=; b=K4bzmiErucRlEUqEBfwmUuCKnSgtIBbAfbA7vCeHaFn6sck4MLX/WeG/Cp6Yfd6lUn zJydRk9IfJBx1VNZuM5n0glKpmG0H9zuobbcNGsQ/k5zkNTaK3XARXS1HNnG7FuwSMDm HY5IJ84Hvix3/2xSP1xgB2qeXa8a34fw085R4RhNAInM1ddwk3FGFOrKT/gjXEVit/Po nCw1chGWK0A2/eo+1ZPGJJs4AoSzZ72ChwvzrHiLp9vNIucKRPuukIm3nJGdgqu7u57u IXl7SxMn7Usnfd0CdVpdqbdNZgxJBa/q5FPP+58Uy3jChi9NsLRc2v6YyLq3UPTMx/ZY sbXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mx1x7WXdWx1OmGiQa8j/Ocnd1yGzb9TNnARrKEjT+x4=; b=X13fo50yqCR9cfFHQpM0d0wWZG4UD8f62JdD+LSzvkT1KZinJ//QTCo5lgJNItgos8 z1ALEfhwG57ahsCIXCBLC8HBpHW2BciVkrbTarer0dr3BDU7m/oxDfNcMp5hnzmDqaIN nk+xNkG/YrmPQMYIXqNlgQH17MNgVTdKxcn18Ko0ye7yRGBS/cqB6MEL+5RD/wmbnOA8 otAou6D0UDjQnSFgbmqLSmnkrNk2qn5q8/nosh3Vgxit2x4O+hE+Rr+HczeCpue4IXGa O/B4loKfCLIHGnYA2ZojT0tqgdSqENC4ozUccqO7l9NOR6dzy9FJoa/NHUx0946x5hJ5 EVcQ== X-Gm-Message-State: AEkoouu5lZyqg++8ztbp3vGPdWLeITJjZb9ONRR1Ik4/wXV2uR3s9iX5zw2rw8SsEgLnGQ== X-Received: by 10.98.59.70 with SMTP id i67mr25785296pfa.45.1470999134831; Fri, 12 Aug 2016 03:52:14 -0700 (PDT) Received: from localhost.localdomain ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id k78sm12034940pfa.78.2016.08.12.03.52.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Aug 2016 03:52:13 -0700 (PDT) From: Keguang Zhang To: linux-clk@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Kelvin Cheung Subject: [PATCH 2/3] clk: Loongson1: Update clocks of Loongson1B Date: Fri, 12 Aug 2016 18:51:47 +0800 Message-Id: <1470999108-9851-3-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470999108-9851-1-git-send-email-keguang.zhang@gmail.com> References: <1470999108-9851-1-git-send-email-keguang.zhang@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kelvin Cheung This patch updates some clock names of Loongson1B, and adds AC97, DMA and NAND clock. Signed-off-by: Kelvin Cheung --- drivers/clk/loongson1/clk-loongson1b.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c index 336ff95..2302ee5 100644 --- a/drivers/clk/loongson1/clk-loongson1b.c +++ b/drivers/clk/loongson1/clk-loongson1b.c @@ -39,19 +39,19 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", }; -static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", }; -static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", }; +static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", }; +static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", }; +static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", }; void __init ls1x_clk_init(void) { struct clk *clk; - clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC); - clk_register_clkdev(clk, "osc_33m_clk", NULL); + clk = clk_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); + clk_register_clkdev(clk, "osc_clk", NULL); /* clock derived from 33 MHz OSC clk */ - clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", + clk = clk_register_pll(NULL, "pll_clk", "osc_clk", &ls1x_pll_clk_ops, 0); clk_register_clkdev(clk, "pll_clk", NULL); @@ -106,6 +106,7 @@ void __init ls1x_clk_init(void) CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock); clk_register_clkdev(clk, "ahb_clk", NULL); + clk_register_clkdev(clk, "ls1x-dma", NULL); clk_register_clkdev(clk, "stmmaceth", NULL); /* clock derived from AHB clk */ @@ -113,9 +114,11 @@ void __init ls1x_clk_init(void) clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, DIV_APB); clk_register_clkdev(clk, "apb_clk", NULL); - clk_register_clkdev(clk, "ls1x_i2c", NULL); - clk_register_clkdev(clk, "ls1x_pwmtimer", NULL); - clk_register_clkdev(clk, "ls1x_spi", NULL); - clk_register_clkdev(clk, "ls1x_wdt", NULL); + clk_register_clkdev(clk, "ls1x-ac97", NULL); + clk_register_clkdev(clk, "ls1x-i2c", NULL); + clk_register_clkdev(clk, "ls1x-nand", NULL); + clk_register_clkdev(clk, "ls1x-pwmtimer", NULL); + clk_register_clkdev(clk, "ls1x-spi", NULL); + clk_register_clkdev(clk, "ls1x-wdt", NULL); clk_register_clkdev(clk, "serial8250", NULL); }