From patchwork Tue Aug 16 07:30:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 9282827 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6A8F960839 for ; Tue, 16 Aug 2016 07:35:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B9DC28919 for ; Tue, 16 Aug 2016 07:35:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4C23228927; Tue, 16 Aug 2016 07:35:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B71C28919 for ; Tue, 16 Aug 2016 07:35:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753322AbcHPHe0 (ORCPT ); Tue, 16 Aug 2016 03:34:26 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:57331 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751694AbcHPHdo (ORCPT ); Tue, 16 Aug 2016 03:33:44 -0400 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 282299876; Tue, 16 Aug 2016 15:32:50 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Tue, 16 Aug 2016 15:32:49 +0800 From: Erin Lo To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring CC: Arnd Bergmann , Sascha Hauer , Daniel Kurtz , Philipp Zabel , , , , , , , Shunli Wang , James Liao , Erin Lo Subject: [PATCH v10 7/9] reset: mediatek: Add MT2701 reset driver Date: Tue, 16 Aug 2016 15:30:27 +0800 Message-ID: <1471332629-15722-8-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471332629-15722-1-git-send-email-erin.lo@mediatek.com> References: <1471332629-15722-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunli Wang In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Signed-off-by: Erin Lo Tested-by: John Crispin Acked-by: Philipp Zabel --- drivers/clk/mediatek/clk-mt2701-hif.c | 2 ++ drivers/clk/mediatek/clk-mt2701.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 33ead83..0ca0537 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -55,6 +55,8 @@ static void mtk_hifsys_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 1, 0x34); } static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index f64dc4e..9dab533 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -791,6 +791,8 @@ static void mtk_infrasys_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 2, 0x30); } static const struct mtk_gate_regs peri0_cg_regs = { @@ -911,6 +913,8 @@ static void mtk_pericfg_init(struct device_node *node) if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); + + mtk_register_reset_controller(node, 2, 0x0); } #define MT8590_PLL_FMAX (2000 * MHZ)