From patchwork Fri Aug 19 05:34:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 9289437 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2BFDF6086A for ; Fri, 19 Aug 2016 05:37:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D31929287 for ; Fri, 19 Aug 2016 05:37:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0EF6029279; Fri, 19 Aug 2016 05:37:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1791429279 for ; Fri, 19 Aug 2016 05:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754259AbcHSFgK (ORCPT ); Fri, 19 Aug 2016 01:36:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:30890 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754799AbcHSFfZ (ORCPT ); Fri, 19 Aug 2016 01:35:25 -0400 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 578219891; Fri, 19 Aug 2016 13:35:22 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 19 Aug 2016 13:35:20 +0800 From: Erin Lo To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring CC: Arnd Bergmann , Sascha Hauer , Daniel Kurtz , Philipp Zabel , , , , , , , James Liao , Erin Lo Subject: [PATCH v11 8/9] arm: dts: mt2701: Add clock controller device nodes Date: Fri, 19 Aug 2016 13:34:55 +0800 Message-ID: <1471584896-9986-9-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471584896-9986-1-git-send-email-erin.lo@mediatek.com> References: <1471584896-9986-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: James Liao Add clock controller nodes for MT2701, include topckgen, infracfg, pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and bdpsys. This patch also add two oscillators that provide clocks for MT2701. Signed-off-by: James Liao Signed-off-by: Erin Lo --- arch/arm/boot/dts/mt2701.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 18596a2..c9a8dbf 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,8 +12,10 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include "skeleton64.dtsi" #include "mt2701-pinfunc.h" @@ -77,6 +79,20 @@ #clock-cells = <0>; }; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + rtc32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; @@ -104,6 +120,26 @@ reg = <0 0x10005000 0 0x1000>; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt2701-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2701-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2701-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; @@ -128,6 +164,12 @@ reg = <0 0x10200100 0 0x1c>; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2701-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller;