From patchwork Mon Aug 22 08:29:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 9293189 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6418E607F0 for ; Mon, 22 Aug 2016 08:31:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53A6228870 for ; Mon, 22 Aug 2016 08:31:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4860D28882; Mon, 22 Aug 2016 08:31:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECBEB28870 for ; Mon, 22 Aug 2016 08:31:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932237AbcHVIaf (ORCPT ); Mon, 22 Aug 2016 04:30:35 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:28049 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753510AbcHVI3k (ORCPT ); Mon, 22 Aug 2016 04:29:40 -0400 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 813378625; Mon, 22 Aug 2016 16:29:36 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Mon, 22 Aug 2016 16:29:35 +0800 From: Erin Lo To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring CC: Arnd Bergmann , Sascha Hauer , Daniel Kurtz , Philipp Zabel , , , , , , , Shunli Wang , James Liao , Erin Lo Subject: [PATCH v12 2/4] reset: mediatek: Add MT2701 reset driver Date: Mon, 22 Aug 2016 16:29:23 +0800 Message-ID: <1471854565-19810-3-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471854565-19810-1-git-send-email-erin.lo@mediatek.com> References: <1471854565-19810-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunli Wang In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Signed-off-by: Erin Lo Tested-by: John Crispin Acked-by: Philipp Zabel --- drivers/clk/mediatek/clk-mt2701-hif.c | 8 ++++++-- drivers/clk/mediatek/clk-mt2701.c | 16 ++++++++++++---- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 18b4ab5..702fd74 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -52,11 +52,15 @@ static int mtk_hifsys_init(struct device_node *node) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return r; + } + + mtk_register_reset_controller(node, 1, 0x34); - return r; + return 0; } static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index f6df578..c8cc583 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -790,11 +790,15 @@ static int mtk_infrasys_init(struct device_node *node) infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return r; + } - return r; + mtk_register_reset_controller(node, 2, 0x30); + + return 0; } static const struct mtk_gate_regs peri0_cg_regs = { @@ -912,11 +916,15 @@ static int mtk_pericfg_init(struct device_node *node) &lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return r; + } - return r; + mtk_register_reset_controller(node, 2, 0x0); + + return 0; } #define MT8590_PLL_FMAX (2000 * MHZ)