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Mon, 22 Aug 2016 17:41:50 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, chanwoo@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chanwoo Choi Subject: [PATCH 1/2] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Date: Mon, 22 Aug 2016 17:41:47 +0900 Message-id: <1471855308-12791-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1471855308-12791-1-git-send-email-cw00.choi@samsung.com> References: <1471855308-12791-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWyRsSkUPf8rl3hBr3POCwm3rjCYnH9y3NW i9cvDC36H79mttj0+Bqrxceee6wWl3fNYbOYcX4fk8XFU64Wh9+0s1r8ONPNYrFq1x9GBx6P 9zda2T0u9/UyeeycdZfdY9OqTjaPzUvqPfq2rGL0+LxJLoA9issmJTUnsyy1SN8ugSvj0buH zAX7uCp2/lvI2MD4maOLkZNDQsBE4sy2M0wQtpjEhXvr2boYuTiEBFYwSpx6/o69i5EDrGjt 1liI+CxGiR+334E1CAl8YZSYci4fxGYT0JLY/+IGG0i9iIChxM1DSiBhZoEFTBIdm8DGCAvE SBxp5AUJswioSuzums0KEuYVcJW4+lIW4gI5iQ97HrGD2JwCbhL9K0+wQixylfi19TYLyAUS AufYJf7PPsUIMUdA4tvkQywQV8pKbDrADDFHUuLgihssExiFFzAyrGIUTS1ILihOSi8y1CtO zC0uzUvXS87P3cQIjI/T/5717mC8fcD6EKMAB6MSDy/Hjl3hQqyJZcWVuYcYTYE2TGSWEk3O B0ZhXkm8obGZkYWpiamxkbmlmZI4r6LUz2AhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjNOD XqTcaMzXPxq8Ou78fJ1G36pzvIevNrCs+qP1tz7R3GXy0gLreLG75tdmr1Mwif/+bGmYaLe4 6hqFppRXPI8cVkcbyzIYbs11/vF3/8d37DPL5/acLDsotGPHueeTbk9m2zwr/X/4+7bMeAbD 42fT+VeuS93jFbxJ3e82i6nha/VF1x6GWCmxFGckGmoxFxUnAgB1QXSnigIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t9jQd3zu3aFG/yYx2wx8cYVFovrX56z Wrx+YWjR//g1s8Wmx9dYLT723GO1uLxrDpvFjPP7mCwunnK1OPymndXix5luFotVu/4wOvB4 vL/Ryu5xua+XyWPnrLvsHptWdbJ5bF5S79G3ZRWjx+dNcgHsUQ2MNhmpiSmpRQqpecn5KZl5 6bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAdyoplCXmlAKFAhKLi5X07TBNCA1x 07WAaYzQ9Q0JgusxMkADCWsYMx69e8hcsI+rYue/hYwNjJ85uhg5OCQETCTWbo3tYuQEMsUk Ltxbz9bFyMUhJDCLUeLH7XdMIAkhgS+MElPO5YPYbAJaEvtf3GAD6RURMJS4eUgJJMwssIBJ omMTO0hYWCBG4kgjL0iYRUBVYnfXbFaQMK+Aq8TVl7IQm+QkPux5xA5icwq4SfSvPMEKschV 4tfW2ywTGHkXMDKsYpRILUguKE5KzzXKSy3XK07MLS7NS9dLzs/dxAiOwWfSOxgP73I/xCjA wajEw8uwcVe4EGtiWXFl7iFGCQ5mJRHeCSAh3pTEyqrUovz4otKc1OJDjKZAd01klhJNzgem h7ySeENjEzMjSyNzQwsjY3Mlcd7H/9eFCQmkJ5akZqemFqQWwfQxcXBKNTAGC9jfazXJyXx2 Zkb7qSftQsJf+G4qhbit1wip/ebL4NvblRI1M+sC39czPM/rU9bsn9uzd1t5jca9zdGzVtee bPx6/HbLfFPB+jnzqm6tm7uF9c3t8weUbNzTfA/KVrgGZu9b5nzK/WjAsoK78/pmPD26QvyO Ukn3O6u/pXaCW9fPX6B4bCGTEktxRqKhFnNRcSIATsFm1dcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) geneates the clocks for DRAM and NoC (Network on Chip) bus clock. Signed-off-by: Chanwoo Choi --- include/dt-bindings/clock/exynos5420.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 17ab8394bec7..6fd21c291416 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -214,6 +214,9 @@ #define CLK_MOUT_SW_ACLK400 651 #define CLK_MOUT_USER_ACLK300_GSCL 652 #define CLK_MOUT_SW_ACLK300_GSCL 653 +#define CLK_MOUT_MCLK_CDREX 654 +#define CLK_MOUT_BPLL 655 +#define CLK_MOUT_MX_MSPLL_CCORE 656 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -239,8 +242,14 @@ #define CLK_DOUT_ACLK300_DISP1 788 #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 +#define CLK_DOUT_PCLK_CDREX 791 +#define CLK_DOUT_SCLK_CDREX 792 +#define CLK_DOUT_ACLK_CDREX1 793 +#define CLK_DOUT_CCLK_DREX0 794 +#define CLK_DOUT_CLK2X_PHY0 795 +#define CLK_DOUT_PCLK_CORE_MEM 796 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 791 +#define CLK_NR_CLKS 797 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */