From patchwork Mon Aug 22 09:19:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9293285 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C4C0607F0 for ; Mon, 22 Aug 2016 09:20:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BDE52870D for ; Mon, 22 Aug 2016 09:20:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E8D128713; Mon, 22 Aug 2016 09:20:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70946286F4 for ; Mon, 22 Aug 2016 09:19:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754862AbcHVJT7 (ORCPT ); Mon, 22 Aug 2016 05:19:59 -0400 Received: from mail-lf0-f44.google.com ([209.85.215.44]:33838 "EHLO mail-lf0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754750AbcHVJT6 (ORCPT ); Mon, 22 Aug 2016 05:19:58 -0400 Received: by mail-lf0-f44.google.com with SMTP id l89so73092307lfi.1 for ; Mon, 22 Aug 2016 02:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uZoV5Ii459hrb6hPGqxe7cdT8o2XChTAZ0EDOzyfqaU=; b=BQ4h6auzUpYjms0olWXp+WqeDTOxpsKmUM9Ewn5GOt2lH7Crvi3dUAvLNR10+qas52 Gs9JtnVv9P/riAl99UbDHl5Vuu83mdn6y15Q6R1FNo2mGEktbpGpBq5LWLyCMyCJ2LHH NJLhWHYWasO/n3lp/rDUVf1V1/ap2o0q/elog= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uZoV5Ii459hrb6hPGqxe7cdT8o2XChTAZ0EDOzyfqaU=; b=YJQPEap4DNuAcr917bbSACZp5QkY8PCYcYINhPvy4IoQA5eSwU06miQZdJaDCWrIMB 7pwoqm9gUtfgnu3hRnpthmBoke1QrarmgiusddzHbotz+ywOLYwuEq9cl2jJOdg6APb/ d0rqcpCIMwUDp+2AOVGC9sgzT77pK3sZdq+022dVAMECOfaP+JaW7jQMtkkI2InFBfem 31kcYi4tWb0O1F3FH4DT+n8CwMsfr35qK8Wk0HTipRpWpPPILHinTDn3U5m665K2nSjk 3Kcr/q7KC9CcbVg4r8pfJA2KFr3Ng4SRvOklgmNC0PWlACenMNYYW1WoXL4dTZq986lr RTbw== X-Gm-Message-State: AEkoouub5+JAEGS+0UM6xenFWR/x9Bp8vaqinxr0RCz0+sxvY5ygm5ma7aKySoMSKBmEGc+z X-Received: by 10.25.133.212 with SMTP id h203mr5737968lfd.28.1471857596568; Mon, 22 Aug 2016 02:19:56 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id 93sm3596854ljb.20.2016.08.22.02.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Aug 2016 02:19:55 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , Russell King Subject: [PATCH 3/3 v2] clk: versatile/icst: support for AP baseboard clocks Date: Mon, 22 Aug 2016 11:19:34 +0200 Message-Id: <1471857574-13125-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1471857574-13125-1-git-send-email-linus.walleij@linaro.org> References: <1471857574-13125-1-git-send-email-linus.walleij@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds support for the two ICST525-based clocks on the Integrator/AP baseboard, as documented in the board manual "Integrator/AP ASIC Development Motherboard", ARM DUI0098 B, pages 3-15 thru 3-18. Cc: Russell King Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Drop DTS patch hunk that need to go into a separate patch. --- drivers/clk/versatile/clk-icst.c | 137 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index 8f06473b72ff..5fd54a6a604e 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -29,15 +29,20 @@ #define VERSATILE_AUX_OSC_BITS 0x7FFFF #define INTEGRATOR_AP_CM_BITS 0xFF +#define INTEGRATOR_AP_SYS_BITS 0xFF #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000 +#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) + /** * enum icst_control_type - the type of ICST control register */ enum icst_control_type { ICST_VERSATILE, /* The standard type, all control bits available */ ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ }; @@ -93,6 +98,38 @@ static int vco_get(struct clk_icst *icst, struct icst_vco *vco) } /* + * The Integrator/AP system clock on the base board can only + * access the low eight bits of the v PLL divider. Bit 8 is tied low + * and always zero, r is hardwired to 46, and the output divider is + * hardwired to 3 (divide by 4) according to the document + * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B, + * page 3-16. + */ + if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { + vco->v = val & INTEGRATOR_AP_SYS_BITS; + vco->r = 46; + vco->s = 3; + return 0; + } + + /* + * The Integrator/AP PCI clock is using an odd pattern to create + * the child clock, basically a single bit called DIVX/Y is used + * to select between two different hardwired values: setting the + * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the + * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies + * 33 or 25 MHz respectively. + */ + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ); + + vco->v = divxy ? 17 : 14; + vco->r = divxy ? 22 : 14; + vco->s = 1; + return 0; + } + + /* * The Integrator/CP core clock can access the low eight bits * of the v PLL divider. Bit 8 is tied low and always zero, * r is hardwired to 22 and the output divider s is accessible @@ -143,6 +180,17 @@ static int vco_set(struct clk_icst *icst, struct icst_vco vco) if (vco.r != 22) pr_err("ICST error: tried to use RDW != 22\n"); break; + case ICST_INTEGRATOR_AP_SYS: + mask = INTEGRATOR_AP_SYS_BITS; + val &= ~0xFF; /* Uses 8 bits */ + val |= vco.v & 0xFF; + if (vco.v & 0x100) + pr_err("ICST error: tried to set bit 8 of VDW\n"); + if (vco.s != 3) + pr_err("ICST error: tried to use VOD != 1\n"); + if (vco.r != 46) + pr_err("ICST error: tried to use RDW != 22\n"); + break; case ICST_INTEGRATOR_CP_CM_CORE: mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */ val = (vco.v & 0xFF) | vco.s << 8; @@ -225,6 +273,27 @@ static long icst_round_rate(struct clk_hw *hw, unsigned long rate, return DIV_ROUND_CLOSEST(rate, 500000) * 500000; } + if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { + /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ + if (rate <= 3000000) + return 3000000; + if (rate >= 50000000) + return 5000000; + /* Slam to closest 0.25 MHz */ + return DIV_ROUND_CLOSEST(rate, 250000) * 250000; + } + + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + /* + * If we're below or less than halfway from 25 to 33 MHz + * select 25 MHz + */ + if (rate <= 25000000 || rate < 29000000) + return 25000000; + /* Else just return the default frequency */ + return 33000000; + } + vco = icst_hz_to_vco(icst->params, rate); return icst_hz(icst->params, vco); } @@ -235,6 +304,36 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_icst *icst = to_icst(hw); struct icst_vco vco; + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + /* This clock is especially primitive */ + unsigned int val; + int ret; + + if (rate == 25000000) { + val = 0; + } else if (rate == 33000000) { + val = INTEGRATOR_AP_PCI_25_33_MHZ; + } else { + pr_err("ICST: cannot set PCI frequency %lu\n", + rate); + return -EINVAL; + } + ret = regmap_write(icst->map, icst->lockreg_off, + VERSATILE_LOCK_VAL); + if (ret) + return ret; + ret = regmap_update_bits(icst->map, icst->vcoreg_off, + INTEGRATOR_AP_PCI_25_33_MHZ, + val); + if (ret) + return ret; + /* This locks the VCO again */ + ret = regmap_write(icst->map, icst->lockreg_off, 0); + if (ret) + return ret; + return 0; + } + if (parent_rate) icst->params->ref = parent_rate; vco = icst_hz_to_vco(icst->params, rate); @@ -368,6 +467,34 @@ static const struct icst_params icst525_apcp_cm_params = { .idx2s = icst525_idx2s, }; +static const struct icst_params icst525_ap_sys_params = { + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, + /* Minimum 3 MHz, VDW = 4 */ + .vd_min = 3, + /* Maximum 50 MHz, VDW = 192 */ + .vd_max = 50, + /* r is hardcoded to 46 and this is the actual divisor, +2 */ + .rd_min = 48, + .rd_max = 48, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, +}; + +static const struct icst_params icst525_ap_pci_params = { + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, + /* Minimum 25 MHz */ + .vd_min = 25, + /* Maximum 33 MHz */ + .vd_max = 33, + /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */ + .rd_min = 16, + .rd_max = 24, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, +}; + static void __init of_syscon_icst_setup(struct device_node *np) { struct device_node *parent; @@ -408,6 +535,12 @@ static void __init of_syscon_icst_setup(struct device_node *np) } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) { icst_desc.params = &icst525_apcp_cm_params; ctype = ICST_INTEGRATOR_AP_CM; + } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) { + icst_desc.params = &icst525_ap_sys_params; + ctype = ICST_INTEGRATOR_AP_SYS; + } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) { + icst_desc.params = &icst525_ap_pci_params; + ctype = ICST_INTEGRATOR_AP_PCI; } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) { icst_desc.params = &icst525_apcp_cm_params; ctype = ICST_INTEGRATOR_CP_CM_CORE; @@ -437,6 +570,10 @@ CLK_OF_DECLARE(arm_syscon_icst307_clk, "arm,syscon-icst307", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk, "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup); +CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk, + "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup); +CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk, + "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk, "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,