From patchwork Tue Aug 23 15:52:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: hotran X-Patchwork-Id: 9295911 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5073F607F0 for ; Tue, 23 Aug 2016 15:55:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 420B428C68 for ; Tue, 23 Aug 2016 15:55:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3703F28CBF; Tue, 23 Aug 2016 15:55:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 644B328C68 for ; Tue, 23 Aug 2016 15:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754031AbcHWPyf (ORCPT ); Tue, 23 Aug 2016 11:54:35 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:36233 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753512AbcHWPxm (ORCPT ); Tue, 23 Aug 2016 11:53:42 -0400 Received: by mail-pa0-f54.google.com with SMTP id di2so1061065pad.3 for ; Tue, 23 Aug 2016 08:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LJvhvqvU2J0lYPhhp8XCZG0Hau5lR0Ew67zCulk3xyw=; b=GRVhN71HTQJ0n66nhj22AtX8YpJglcADbvf2Z694xHSOyh90fWSwM60/E0jLh7q+Jr 1sgLF7eLMe49kUuth011LUwSk2K7Pz55tFbboUqQxVo/rgTORHgrneSz1CluxXxSQT1B 9hz+pX2CJwUp9BpJYJxRaj1jwLg7fq1drjPEk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LJvhvqvU2J0lYPhhp8XCZG0Hau5lR0Ew67zCulk3xyw=; b=GfLjg6oC+/Qyj6XzpvaBGsE+azdxocPOE+QKybDZUsMaxOzkYvLu/XIjNwjqL/EZJ3 XvWqwTRPAhtyUbbWuzESUDrOJhiZpTE0/YBaFdZfs5fcYGAEHFeNFYhJ+ogifKTlftqh QlWD2bgn6T9heBCrfCEK8gJYFHsSWcpXLdWMk/hB+Y2ZhHQ8bnl0dQ5yftdghuJVINGG LN4MR1VwyETDTd6bkz2jGb/uqWOI5etOOHcZRSzwLgRXjBw2s2h5FVfraHQ/6uSerTQa 3M9YRVCkchitIxixO065Hp2DBKTnzj/0z0Wpryk/4jf+BhX6ay9UqnTU+ywv1VF5hsuA 7EMQ== X-Gm-Message-State: AEkooutPW6hsN9pP0Hfup9/BoIUNQUFBaWBP9lEfvvMLSNZvJfdJAQf/jMNZo3/lHHkZgQDq X-Received: by 10.66.177.7 with SMTP id cm7mr54634432pac.132.1471967616749; Tue, 23 Aug 2016 08:53:36 -0700 (PDT) Received: from hotran_localhost.amcc.com ([206.80.4.98]) by smtp.gmail.com with ESMTPSA id s89sm6765178pfi.83.2016.08.23.08.53.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Aug 2016 08:53:36 -0700 (PDT) From: Hoan Tran To: Michael Turquette , Rob Herring , Stephen Boyd , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lho@apm.com, Duc Dang , Hoan Tran Subject: [PATCH 1/3] Documentation: dtb: xgene: Add PMD clock binding Date: Tue, 23 Aug 2016 08:52:39 -0700 Message-Id: <1471967561-23634-2-git-send-email-hotran@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471967561-23634-1-git-send-email-hotran@apm.com> References: <1471967561-23634-1-git-send-email-hotran@apm.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add APM X-Gene clock binding documentation for PMD clock. Signed-off-by: Hoan Tran --- Documentation/devicetree/bindings/clock/xgene.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt index 82f9638..c381733 100644 --- a/Documentation/devicetree/bindings/clock/xgene.txt +++ b/Documentation/devicetree/bindings/clock/xgene.txt @@ -8,6 +8,7 @@ Required properties: - compatible : shall be one of the following: "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock + "apm,xgene-pmd-clock" - for a X-Gene PMD clock "apm,xgene-device-clock" - for a X-Gene device clock "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock @@ -22,6 +23,17 @@ Required properties for SoC or PCP PLL clocks: Optional properties for PLL clocks: - clock-names : shall be the name of the PLL. If missing, use the device name. +Required properties for PMD clocks: +- reg : shall be the physical register address for the pmd clock. +- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the clock referenced by derive + clock. +- clock-shift: Bit shift of the clock register. Default is 0. +- clock-width: Width of the clock register. Default is 32. +Optional properties for PLL clocks: +- clock-names : shall be the name of the clock. If missing, use the device name. + Required properties for device clocks: - reg : shall be a list of address and length pairs describing the CSR reset and/or the divider. Either may be omitted, but at least @@ -59,6 +71,16 @@ For example: type = <0>; }; + pmd0clk: pmd0clk { + compatible = "apm,xgene-pmd-clock"; + #clock-cells = <1>; + clocks = <&pmdpll 0>; + reg = <0x0 0x7E200200 0x0 0x10>; + clock-shift = <8>; + clock-width = <3>; + clock-output-names = "pmd0clk"; + }; + socpll: socpll@17000120 { compatible = "apm,xgene-socpll-clock"; #clock-cells = <1>;