diff mbox

[v2,1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller)

Message ID 1472108238-24309-2-git-send-email-cw00.choi@samsung.com (mailing list archive)
State Not Applicable, archived
Delegated to: Stephen Boyd
Headers show

Commit Message

Chanwoo Choi Aug. 25, 2016, 6:57 a.m. UTC
This patch adds the new clock id for CMU_CDRES (DRAM Express Controller)
geneates the clocks for DRAM and NoC (Network on Chip) bus clock.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 include/dt-bindings/clock/exynos5420.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

Comments

On 08/25/2016 08:57 AM, Chanwoo Choi wrote:
> This patch adds the new clock id for CMU_CDRES (DRAM Express Controller)
> geneates the clocks for DRAM and NoC (Network on Chip) bus clock.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

Applied with the commit message changed as below, thanks.

commit 9c605fbc299d31b482aefae547d126062c7a8792
Author: Chanwoo Choi <cw00.choi@samsung.com>
Date:   Thu Aug 25 15:57:16 2016 +0900

 dt-bindings: Add clock IDs for the CMU_CDREX (DRAM Express Controller)

 This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller)
 which generates clocks for DRAM and NoC (Network on Chip) busses.

 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
 Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>



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diff mbox

Patch

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 17ab8394bec7..6fd21c291416 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -214,6 +214,9 @@ 
 #define CLK_MOUT_SW_ACLK400     651
 #define CLK_MOUT_USER_ACLK300_GSCL	652
 #define CLK_MOUT_SW_ACLK300_GSCL	653
+#define CLK_MOUT_MCLK_CDREX	654
+#define CLK_MOUT_BPLL		655
+#define CLK_MOUT_MX_MSPLL_CCORE	656
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
@@ -239,8 +242,14 @@ 
 #define CLK_DOUT_ACLK300_DISP1	788
 #define CLK_DOUT_ACLK300_GSCL	789
 #define CLK_DOUT_ACLK400_DISP1	790
+#define CLK_DOUT_PCLK_CDREX	791
+#define CLK_DOUT_SCLK_CDREX	792
+#define CLK_DOUT_ACLK_CDREX1	793
+#define CLK_DOUT_CCLK_DREX0	794
+#define CLK_DOUT_CLK2X_PHY0	795
+#define CLK_DOUT_PCLK_CORE_MEM	796
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		791
+#define CLK_NR_CLKS		797
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */