Message ID | 1472124047-22627-1-git-send-email-srinivas.kandagatla@linaro.org (mailing list archive) |
---|---|
State | Accepted, archived |
Delegated to: | Stephen Boyd |
Headers | show |
On 08/25, Srinivas Kandagatla wrote: > This patch corrects the register offset for pcie2 pipe clock. > Offset according to datasheet is 0x6e018 instead of 0x6e108. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > --- Applied to clk-next
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index a1ef12f..456b2f4 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { }; static struct clk_branch gcc_pcie_2_pipe_clk = { - .halt_reg = 0x6e108, + .halt_reg = 0x6e018, .clkr = { - .enable_reg = 0x6e108, + .enable_reg = 0x6e018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk",
This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- drivers/clk/qcom/gcc-msm8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)