From patchwork Thu Aug 25 11:20:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 9299237 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3FA5C607D8 for ; Thu, 25 Aug 2016 11:21:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3176D29201 for ; Thu, 25 Aug 2016 11:21:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 25D7229204; Thu, 25 Aug 2016 11:21:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE64929203 for ; Thu, 25 Aug 2016 11:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757301AbcHYLVG (ORCPT ); Thu, 25 Aug 2016 07:21:06 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:36883 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757323AbcHYLVE (ORCPT ); Thu, 25 Aug 2016 07:21:04 -0400 Received: by mail-wm0-f43.google.com with SMTP id i5so66578951wmg.0 for ; Thu, 25 Aug 2016 04:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=XVd01UrmxlYn79ud3wZChboww7l2i3kqKqueeNnuv5g=; b=SiT/IkgtqFsySWcdDCfixSLQClWhaMoD+lYOLZYcTzhQiUNY2lJq/Uxjw5tHB/qNkJ Xg1f+isvZlyY9k2txOS96kCvYJDDibmt/r7UZdd+qRq9VIjvG4ImnlYBzVR8re8hSMu6 6WGyn7/2tu866BdNdjQc7P8o6qU7cWirp/tfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XVd01UrmxlYn79ud3wZChboww7l2i3kqKqueeNnuv5g=; b=ReyW3abz0U8/lHs2aTjLUilkLXbY6HjLtZQB+8mSUSTAQmhC/pJyiPJVP4FjHG6bro owUoBUbYA4RMBf7HDUit/60m/17Twa5NVvOdQUZSDhpI4iuCiRwSv5CSGQM5b5gq09qX KvmbDLwK1XqXIHaTTaXe9lfA+NC6EavQsoAm8T5/yX2CFcHa/jxxeBiy6BtFupWSRR5h osnQSU9VOAS1sOTU6wIrFn+NWIy8XY6+k805b/p37a/r4qpTvL50VIi/Q0ah+o7dLNP4 EUZSqI6qbXNQ1eyU9Y2TsBrorQ7rQUvnSL8zaaxv6u6WY5w8KoFmetC3ux6JxbsYVYSL 5zZA== X-Gm-Message-State: AE9vXwMu3Y7+FwS0XKhU2PUo0t3pAxRwU/YHCqJntPzyjDs3uq+tTEnw3BALYgpidXQiHk1e X-Received: by 10.28.12.76 with SMTP id 73mr7306712wmm.118.1472124063378; Thu, 25 Aug 2016 04:21:03 -0700 (PDT) Received: from localhost.localdomain (host-2-103-180-164.as13285.net. [2.103.180.164]) by smtp.gmail.com with ESMTPSA id o4sm14643695wjd.15.2016.08.25.04.21.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Aug 2016 04:21:02 -0700 (PDT) From: Srinivas Kandagatla To: Stephen Boyd Cc: Andy Gross , David Brown , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/2] clk: gcc-msm8996: Fix pcie 2 pipe register offset Date: Thu, 25 Aug 2016 12:20:46 +0100 Message-Id: <1472124047-22627-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/gcc-msm8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index a1ef12f..456b2f4 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { }; static struct clk_branch gcc_pcie_2_pipe_clk = { - .halt_reg = 0x6e108, + .halt_reg = 0x6e018, .clkr = { - .enable_reg = 0x6e108, + .enable_reg = 0x6e018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk",