From patchwork Tue Sep 6 12:04:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9316479 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7D449607D3 for ; Tue, 6 Sep 2016 12:05:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EA5B28C67 for ; Tue, 6 Sep 2016 12:05:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6351228CF4; Tue, 6 Sep 2016 12:05:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A005128C67 for ; Tue, 6 Sep 2016 12:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933446AbcIFMFj (ORCPT ); Tue, 6 Sep 2016 08:05:39 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:38382 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932721AbcIFMFh (ORCPT ); Tue, 6 Sep 2016 08:05:37 -0400 Received: from epcpsbgm1new.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OD3000R4092W1D0@mailout3.samsung.com>; Tue, 06 Sep 2016 21:05:36 +0900 (KST) X-AuditID: cbfee61a-f78ff6d000001462-2c-57ceb10f53dc Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id E6.CF.05218.F01BEC75; Tue, 6 Sep 2016 21:05:36 +0900 (KST) Received: from AMDC1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OD300B5A08TSS80@mmp2.samsung.com>; Tue, 06 Sep 2016 21:05:35 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, Sylwester Nawrocki Subject: [PATCH v2 3/7] clk: samsung: Use common registration function for pll2550x Date: Tue, 06 Sep 2016 14:04:52 +0200 Message-id: <1473163496-17820-4-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1473163496-17820-1-git-send-email-s.nawrocki@samsung.com> References: <1473163496-17820-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgluLIzCtJLcpLzFFi42I5/e+xoK7AxnPhBjs/MllsnLGe1eL8+Q3s Fh977rFazDi/j8ni8Jt2VgdWj02rOtk8+rasYvT4vEkugDmKyyYlNSezLLVI3y6BK+Np3wum gm/qFSfu1TYwLlTsYuTkkBAwkWhbepsFwhaTuHBvPVsXIxeHkMAsRondN5pZIZxfjBLvTnaw g1SxCRhK9B7tYwSxRQQcJHYdm8wEYjMLxEg03p4FZgsLhEpMfvgfaBIHB4uAqsTriywgJq+A m8SF19IQu+QkTh6bzApicwq4S8w+0wtmCwGVrH92n3kCI+8CRoZVjBKpBckFxUnpuYZ5qeV6 xYm5xaV56XrJ+bmbGMHh8kxqB+PBXe6HGAU4GJV4eA+eOxsuxJpYVlyZe4hRgoNZSYTXb825 cCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8j/+vCxMSSE8sSc1OTS1ILYLJMnFwSjUwClaKz9+j c4PxePcahYykoiT1vWy1Agt3/svb7rXzYb15yKlFStPU/Tglqmaqytn8LNOfFGFerS71+1h5 5+YZnm941gbPZvyzVe8pl2P1U9eebTbbV83+E5G4NiL3Rdn8SScPr9R+bzenJ/CO7onvMqoM fxdt6b0gd9zhhWlAzCaGZ99dcznfK7EUZyQaajEXFScCAPB64gITAgAA Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is no such significant differences in pll2550x PLL type to justify a separate registration function. This patch adapts exynos5440 driver to use the common function and removes samsung_clk_register_pll2550x(). Signed-off-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi --- This patch is untested as I don't have access to any exynos5440 SoC based board. --- drivers/clk/samsung/clk-exynos5440.c | 9 ++++-- drivers/clk/samsung/clk-pll.c | 52 ++++------------------------------ drivers/clk/samsung/clk-pll.h | 1 + include/dt-bindings/clock/exynos5440.h | 2 ++ 4 files changed, 15 insertions(+), 49 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index a57d01b..a80f3ef 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -112,6 +112,11 @@ static struct notifier_block exynos5440_clk_restart_handler = { .priority = 128, }; +static const struct samsung_pll_clock exynos5440_plls[] __initconst = { + PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL), + PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), +}; + /* register exynos5440 clocks */ static void __init exynos5440_clk_init(struct device_node *np) { @@ -129,8 +134,8 @@ static void __init exynos5440_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); - samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); + samsung_clk_register_pll(ctx, exynos5440_plls, + ARRAY_SIZE(exynos5440_plls), ctx->reg_base); samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, ARRAY_SIZE(exynos5440_fixed_rate_clks)); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 48139bd..b5ab055 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -890,22 +890,14 @@ static const struct clk_ops samsung_s3c2440_mpll_clk_ops = { #define PLL2550X_M_SHIFT (4) #define PLL2550X_S_SHIFT (0) -struct samsung_clk_pll2550x { - struct clk_hw hw; - const void __iomem *reg_base; - unsigned long offset; -}; - -#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw) - static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw); + struct samsung_clk_pll *pll = to_clk_pll(hw); u32 r, p, m, s, pll_stat; u64 fvco = parent_rate; - pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3); + pll_stat = readl_relaxed(pll->con_reg); r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; if (!r) return 0; @@ -923,43 +915,6 @@ static const struct clk_ops samsung_pll2550x_clk_ops = { .recalc_rate = samsung_pll2550x_recalc_rate, }; -struct clk * __init samsung_clk_register_pll2550x(const char *name, - const char *pname, const void __iomem *reg_base, - const unsigned long offset) -{ - struct samsung_clk_pll2550x *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) { - pr_err("%s: could not allocate pll clk %s\n", __func__, name); - return NULL; - } - - init.name = name; - init.ops = &samsung_pll2550x_clk_ops; - init.flags = CLK_GET_RATE_NOCACHE; - init.parent_names = &pname; - init.num_parents = 1; - - pll->hw.init = &init; - pll->reg_base = reg_base; - pll->offset = offset; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) { - pr_err("%s: failed to register pll clock %s\n", __func__, - name); - kfree(pll); - } - - if (clk_register_clkdev(clk, name, NULL)) - pr_err("%s: failed to register lookup for %s", __func__, name); - - return clk; -} - /* * PLL2550xx Clock Type */ @@ -1263,6 +1218,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_s3c2440_mpll_clk_ops; break; + case pll_2550x: + init.ops = &samsung_pll2550x_clk_ops; + break; case pll_2550xx: if (!pll->rate_table) init.ops = &samsung_pll2550xx_clk_min_ops; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 213de9a..df4ad8a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -31,6 +31,7 @@ enum samsung_pll_type { pll_s3c2410_mpll, pll_s3c2410_upll, pll_s3c2440_mpll, + pll_2550x, pll_2550xx, pll_2650xx, pll_1450x, diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h index c66fc40..842cdc0 100644 --- a/include/dt-bindings/clock/exynos5440.h +++ b/include/dt-bindings/clock/exynos5440.h @@ -14,6 +14,8 @@ #define CLK_XTAL 1 #define CLK_ARM_CLK 2 +#define CLK_CPLLA 3 +#define CLK_CPLLB 4 #define CLK_SPI_BAUD 16 #define CLK_PB0_250 17 #define CLK_PR0_250 18