From patchwork Thu Sep 8 07:01:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 9320455 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EF82B60752 for ; Thu, 8 Sep 2016 07:01:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8ED2295D9 for ; Thu, 8 Sep 2016 07:01:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD4CC295E0; Thu, 8 Sep 2016 07:01:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.4 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAFC4295DD for ; Thu, 8 Sep 2016 07:01:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932915AbcIHHBM (ORCPT ); Thu, 8 Sep 2016 03:01:12 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:34949 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932520AbcIHHBK (ORCPT ); Thu, 8 Sep 2016 03:01:10 -0400 Received: by mail-wm0-f65.google.com with SMTP id a6so6377430wmc.2 for ; Thu, 08 Sep 2016 00:01:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=n9OSLWLPBAKilR9JH2AtTWz7pycl7gVIZyDEuKTT20c=; b=RWZ/wewnQZtabiq927GUAkil2kevLPte1Jh34G+HPG/ZkWX/DAMlDlk6c7Jo9BVjZo 5B7kL1dniG24rNbijONsK9gJtaj6KynqHt2Zzo22dmoew6L7s19NVImr5itW0wiTlaKj kVT6jkXW1cklJqNqsSRIRLbGFKcQM0hQOASrx0XAEMyQe+aPNMpfESFc7WCesNire+Yr JP+Qc2MNXV6K8cuqOdfB3bgid191K7W8uTMSFzmFmrcppgxd2EjOO83jhaRqtI3ls+gn +eOafzY/1gIaroEDVVvPrygcxpK4YalIvaUQ+UVFL1vcZFGD7NUpqNUENdIAdFfE6JOL qR0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=n9OSLWLPBAKilR9JH2AtTWz7pycl7gVIZyDEuKTT20c=; b=d/o87GYfzsl7SfKwsUkmJOzDY22tq8X2hc/2AKCYWBsL60xvsc8xcrBbCzqb2N7zTf MCPRx7yXiJjR9oyrDeXs1IMm5jq4UaW3ei1wyoTSnOlcRVPZY2WSQBJZfTCxs83zPQHl jsdSzX1fqvMzhyvx5tHF0ouL4JkTWhGFuZ212Y/mo/JiKCjOh01cv+ZihTp0/jWWgHJl K5Xa/Glv+QJaC4kFoqd9spKas8Tdqur4hknudNpmrCHSzmmEcYGsY0wOoKm+N5mkP8EC 0GONKomBaB7ijL/xpw2X8yZynZE5OiPleaMWXseonC2u5didiayo+O0B2VtabQ8f8bOD R+pQ== X-Gm-Message-State: AE9vXwPkO8WerQ9mkOp35K30U4j/VWytgpJK0bxXmMz19bJweW9tX/7/MFbOrJbjZphrkw== X-Received: by 10.194.80.104 with SMTP id q8mr51247925wjx.151.1473318068692; Thu, 08 Sep 2016 00:01:08 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.googlemail.com with ESMTPSA id 1sm2052485wmm.0.2016.09.08.00.01.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Sep 2016 00:01:07 -0700 (PDT) From: Andrea Merello To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Andrea Merello , Michael Turquette , Stephen Boyd , Maxime Coquelin , Alexandre Torgue , Bruno Herrera Subject: [PATCH] clk: stm32f4: don't assume 48MHz clock is derived from primary PLL Date: Thu, 8 Sep 2016 09:01:03 +0200 Message-Id: <1473318063-21782-1-git-send-email-andrea.merello@gmail.com> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This driver just look at the PLLs configurations set by the bootloader, but it assumes the 48MHz clock is derived from the primary PLL; however using PLLSAI is another option for generating the 48MHz clock. This patch make the driver to check for this, and eventually adjust the clock tree accordingly Signed-off-by: Andrea Merello Cc: Michael Turquette Cc: Stephen Boyd Cc: Maxime Coquelin Cc: Alexandre Torgue Cc: Bruno Herrera --- drivers/clk/clk-stm32f4.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 02d6810..7f1ba8f 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -24,6 +24,7 @@ #include #include +#define STM32F4_RCC_CR 0x00 #define STM32F4_RCC_PLLCFGR 0x04 #define STM32F4_RCC_CFGR 0x08 #define STM32F4_RCC_AHB1ENR 0x30 @@ -31,6 +32,8 @@ #define STM32F4_RCC_AHB3ENR 0x38 #define STM32F4_RCC_APB1ENR 0x40 #define STM32F4_RCC_APB2ENR 0x44 +#define STM32F4_RCC_PLLSAICFGR 0x88 +#define STM32F4_RCC_DCKCFGR 0x8C struct stm32f4_gate_data { u8 offset; @@ -238,16 +241,35 @@ static struct clk *clk_register_apb_mul(struct device *dev, const char *name, static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk) { unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR); - + unsigned long pllsaicfgr = readl(base + STM32F4_RCC_PLLSAICFGR); + unsigned long dckcfgr = readl(base + STM32F4_RCC_DCKCFGR); + unsigned long rcccr = readl(base + STM32F4_RCC_CR); + bool saien = rcccr & BIT(28); unsigned long pllm = pllcfgr & 0x3f; unsigned long plln = (pllcfgr >> 6) & 0x1ff; unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1); const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk; unsigned long pllq = (pllcfgr >> 24) & 0xf; + bool src48_sai = dckcfgr & BIT(27); + unsigned long pllsain = (pllsaicfgr >> 6) & 0x1ff; + unsigned long pllsaip = BIT(((pllsaicfgr >> 16) & 3) + 1); clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm); clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp); - clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); + + if (src48_sai && !saien) { + pr_err("48MHz derived from SAI PLL, but SAI PLL disabled (blame the bootloader)\n"); + return; + } + + if (saien) + clk_register_fixed_factor(NULL, "sai", + pllsrc, 0, pllsain, pllm); + + if (src48_sai) + clk_register_fixed_factor(NULL, "pll48", "sai", 0, 1, pllsaip); + else + clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); } /*