From patchwork Mon Sep 19 04:38:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keguang Zhang X-Patchwork-Id: 9338515 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4FE126077A for ; Mon, 19 Sep 2016 04:40:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4155C28DA6 for ; Mon, 19 Sep 2016 04:40:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3498328F7C; Mon, 19 Sep 2016 04:40:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A049828DA6 for ; Mon, 19 Sep 2016 04:40:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936667AbcISEjb (ORCPT ); Mon, 19 Sep 2016 00:39:31 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:34450 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753181AbcISEjT (ORCPT ); Mon, 19 Sep 2016 00:39:19 -0400 Received: by mail-pf0-f193.google.com with SMTP id 21so5207117pfy.1; Sun, 18 Sep 2016 21:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UiYXnR92dhV3Mg13T/UdvGJOqhA752FyOSS9fnJs7aU=; b=uyDfb4PH4gBXvHA4QJKtdZuxt+puVX4ZjFr2EsoBXFgRgelQ/dXkVT+20aYByv9iYh JXnuNgdDeBB9Hkn9DvoYe6sXeCBPMDeYr9+fg69uvvP3ayMYRPbrw2cOei/RPa/ueYBO HDXvzJ5eR3FSl7GHDEp2gLwik4HxF6MHqTYW0Du3VBv2E1GuZUP0p4vKp1682T5fvOu2 7wF5ge+g1HuTn1pnuPLEUSD5++TvQNuKspE4B+dmu1EdRcDItr2qqcO12C1DldoTtplB rY4pHE4k5Xoy7kIgL2eWVWap7rzJP7eUiQn67iiBSoOCHaUATNGU7WOHA1RWMgzA6qhF EEcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UiYXnR92dhV3Mg13T/UdvGJOqhA752FyOSS9fnJs7aU=; b=bQfteSsQfi7DelTzspTxTTuOhwrGm+QOYltsxI1XeG7M2C9+LAgRtTAHeqXvqvMSOD YGB+/aQfFfN8RkkyLivIQMWFHsO5guS4c9/L8wU8fN+YMRR4xXicIoRz6/5MZ0lPHGMA qWCKDIuG91SPr7n0spNYtohMLg2/pSS2FXOuP/E+G8NxH1b9oSwV+jAEYZCStpQe2V9b SIj9+Le8AviO2fX5IEjaBz27QJ3VwgrpRUC43TRGYJ+lxgpfpyp5q6uwkbrE2XXRvbn9 O20A8nz+ZaKsDOIOZCYpD83lph18VtRLlgwqhMKy/Op1MNaStN/5rhKpWYDy4Tp51n1X ICHA== X-Gm-Message-State: AE9vXwPaISZpcRdZ2iHqV19oRxaM9DcD9B1c4o5iy3nGhXt90AKURQG3xBCN1+cWBu4b8A== X-Received: by 10.98.64.193 with SMTP id f62mr43228632pfd.141.1474259958185; Sun, 18 Sep 2016 21:39:18 -0700 (PDT) Received: from localhost.localdomain ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id p7sm19598950paa.3.2016.09.18.21.39.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Sep 2016 21:39:17 -0700 (PDT) From: Keguang Zhang To: linux-clk@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Kelvin Cheung Subject: [PATCH V1 1/3] clk: Loongson1: Refactor Loongson1 clock Date: Mon, 19 Sep 2016 12:38:54 +0800 Message-Id: <1474259936-9657-2-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1474259936-9657-1-git-send-email-keguang.zhang@gmail.com> References: <1474259936-9657-1-git-send-email-keguang.zhang@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kelvin Cheung Factor out the common functions into loongson1/clk.c to support both Loongson1B and Loongson1C. And, put the rest into loongson1/clk-loongson1b.c. Signed-off-by: Kelvin Cheung --- v1: Rebase the patch on clk: ls1x: Migrate to clk_hw based OF and registration APIs. --- drivers/clk/Makefile | 2 +- drivers/clk/loongson1/Makefile | 2 + .../clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} | 51 ++-------------------- drivers/clk/loongson1/clk.c | 43 ++++++++++++++++++ drivers/clk/loongson1/clk.h | 19 ++++++++ 5 files changed, 69 insertions(+), 48 deletions(-) create mode 100644 drivers/clk/loongson1/Makefile rename drivers/clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} (78%) create mode 100644 drivers/clk/loongson1/clk.c create mode 100644 drivers/clk/loongson1/clk.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8264d81..925081e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o -obj-$(CONFIG_MACH_LOONGSON32) += clk-ls1x.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o @@ -61,6 +60,7 @@ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/ obj-$(CONFIG_MACH_INGENIC) += ingenic/ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ +obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/ obj-$(CONFIG_MACH_PIC32) += microchip/ diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile new file mode 100644 index 0000000..5a162a1 --- /dev/null +++ b/drivers/clk/loongson1/Makefile @@ -0,0 +1,2 @@ +obj-y += clk.o +obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/loongson1/clk-loongson1b.c similarity index 78% rename from drivers/clk/clk-ls1x.c rename to drivers/clk/loongson1/clk-loongson1b.c index 8430e45..5b6817e 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/loongson1/clk-loongson1b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 Zhang, Keguang + * Copyright (c) 2012-2016 Zhang, Keguang * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -10,25 +10,16 @@ #include #include #include -#include #include #include +#include "clk.h" #define OSC (33 * 1000000) #define DIV_APB 2 static DEFINE_SPINLOCK(_lock); -static int ls1x_pll_clk_enable(struct clk_hw *hw) -{ - return 0; -} - -static void ls1x_pll_clk_disable(struct clk_hw *hw) -{ -} - static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -43,44 +34,9 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, } static const struct clk_ops ls1x_pll_clk_ops = { - .enable = ls1x_pll_clk_enable, - .disable = ls1x_pll_clk_disable, .recalc_rate = ls1x_pll_recalc_rate, }; -static struct clk_hw *__init clk_hw_register_pll(struct device *dev, - const char *name, - const char *parent_name, - unsigned long flags) -{ - int ret; - struct clk_hw *hw; - struct clk_init_data init; - - /* allocate the divider */ - hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL); - if (!hw) { - pr_err("%s: could not allocate clk_hw\n", __func__); - return ERR_PTR(-ENOMEM); - } - - init.name = name; - init.ops = &ls1x_pll_clk_ops; - init.flags = flags | CLK_IS_BASIC; - init.parent_names = (parent_name ? &parent_name : NULL); - init.num_parents = (parent_name ? 1 : 0); - hw->init = &init; - - /* register the clock */ - ret = clk_hw_register(dev, hw); - if (ret) { - kfree(hw); - hw = ERR_PTR(ret); - } - - return hw; -} - static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", }; static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", }; static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", }; @@ -93,7 +49,8 @@ void __init ls1x_clk_init(void) clk_hw_register_clkdev(hw, "osc_33m_clk", NULL); /* clock derived from 33 MHz OSC clk */ - hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0); + hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", + &ls1x_pll_clk_ops, 0); clk_hw_register_clkdev(hw, "pll_clk", NULL); /* clock derived from PLL clk */ diff --git a/drivers/clk/loongson1/clk.c b/drivers/clk/loongson1/clk.c new file mode 100644 index 0000000..cfcfd14 --- /dev/null +++ b/drivers/clk/loongson1/clk.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2012-2016 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +struct clk_hw *__init clk_hw_register_pll(struct device *dev, + const char *name, + const char *parent_name, + const struct clk_ops *ops, + unsigned long flags) +{ + int ret; + struct clk_hw *hw; + struct clk_init_data init; + + /* allocate the divider */ + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + hw->init = &init; + + /* register the clock */ + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(hw); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/loongson1/clk.h b/drivers/clk/loongson1/clk.h new file mode 100644 index 0000000..085d74b --- /dev/null +++ b/drivers/clk/loongson1/clk.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2012-2016 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __LOONGSON1_CLK_H +#define __LOONGSON1_CLK_H + +struct clk_hw *clk_hw_register_pll(struct device *dev, + const char *name, + const char *parent_name, + const struct clk_ops *ops, + unsigned long flags); + +#endif /* __LOONGSON1_CLK_H */