From patchwork Mon Sep 19 04:38:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keguang Zhang X-Patchwork-Id: 9338505 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C8F9660B16 for ; Mon, 19 Sep 2016 04:39:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BAD4528DA6 for ; Mon, 19 Sep 2016 04:39:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE1C228FAB; Mon, 19 Sep 2016 04:39:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 456F228EA2 for ; Mon, 19 Sep 2016 04:39:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936424AbcISEj1 (ORCPT ); Mon, 19 Sep 2016 00:39:27 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34960 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934266AbcISEjW (ORCPT ); Mon, 19 Sep 2016 00:39:22 -0400 Received: by mail-pf0-f195.google.com with SMTP id 6so3687814pfl.2; Sun, 18 Sep 2016 21:39:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=psKvUvbn2gDx+BqanHU13UX+68fBJlwPN9X2+ucFxqY=; b=1C5AESFw+C/UG7wsWTFuRijPMLuFb05Yj6A1e+b16TZLT03Q/E61SNnKv9VVmxJ8BW /8l0i2h9xMCJsd1x94hlydmjg3A3UMEHv1QiDMM7J67T7q8eNVBfaazH5f5rXlNHbC4x W4xpKBCZ42VPJG6go9paTAE9oqQSkwM31Pv03N4qVOSpZqy6KOaTn1p0GUSo0EwDhbkg brt5xXnlMXuarWw8PorRkOzTXDWypNkHawRnQv4NCLS3tMf/pccGaVft0gWfqQOkT2vA RbPM7AJzn2l+zm01e0xEfiag/1sZBgcPcFamKK3xF+JiEcB+JONywMrb2LgSnjlbWevm hAOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=psKvUvbn2gDx+BqanHU13UX+68fBJlwPN9X2+ucFxqY=; b=V7PYr777hzzUJvIW73OyRkIET/9fBpIzP4Hxa2ixpVTZfDBIDbUYub7d8T6FL4Lh0o O8tfeBbggxpjIckGP1rauzpA1FuCMzyBNn/Z1+LT7aKa7rIDXuK3WkOYsbXAx08Bq6gE KdE9ZGNyOZmYtpPcoYZAu7UhuXHStR8CWLNhDDD8JQyb8aWuEZrhAwug7Y1pqgKhK4h3 fTZnaSc93mX5bk00W2yNJ/Md2Cw2128MmdffuBItTvyqEG6Gdb8LTeC5cD1KxpWXAz4X 1tgE/Lk6GJaHVOykZw/g++XFcxluYLo1Ojzire3boU2ssLO+QJxCaxyx2SqSio31hNYB Qe9Q== X-Gm-Message-State: AE9vXwPq78s7HBE7Uu5aos943C9Y65ZdRqBcRBrwpu8moyA1qJwbskWAfMhQC6Coqg2xPA== X-Received: by 10.98.64.93 with SMTP id n90mr43535547pfa.29.1474259961492; Sun, 18 Sep 2016 21:39:21 -0700 (PDT) Received: from localhost.localdomain ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id p7sm19598950paa.3.2016.09.18.21.39.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Sep 2016 21:39:20 -0700 (PDT) From: Keguang Zhang To: linux-clk@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Kelvin Cheung Subject: [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B Date: Mon, 19 Sep 2016 12:38:55 +0800 Message-Id: <1474259936-9657-3-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1474259936-9657-1-git-send-email-keguang.zhang@gmail.com> References: <1474259936-9657-1-git-send-email-keguang.zhang@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kelvin Cheung This patch updates some clock names of Loongson1B, and adds AC97, DMA and NAND clock. Signed-off-by: Kelvin Cheung --- v1: Rebase the patch on clk: ls1x: Migrate to clk_hw based OF and registration APIs. --- drivers/clk/loongson1/clk-loongson1b.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c index 5b6817e..4b3d9d2 100644 --- a/drivers/clk/loongson1/clk-loongson1b.c +++ b/drivers/clk/loongson1/clk-loongson1b.c @@ -37,19 +37,19 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", }; -static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", }; -static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", }; +static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", }; +static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", }; +static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", }; void __init ls1x_clk_init(void) { struct clk_hw *hw; - hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC); - clk_hw_register_clkdev(hw, "osc_33m_clk", NULL); + hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); + clk_hw_register_clkdev(hw, "osc_clk", NULL); /* clock derived from 33 MHz OSC clk */ - hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", + hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk", &ls1x_pll_clk_ops, 0); clk_hw_register_clkdev(hw, "pll_clk", NULL); @@ -104,6 +104,7 @@ void __init ls1x_clk_init(void) CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock); clk_hw_register_clkdev(hw, "ahb_clk", NULL); + clk_hw_register_clkdev(hw, "ls1x-dma", NULL); clk_hw_register_clkdev(hw, "stmmaceth", NULL); /* clock derived from AHB clk */ @@ -111,9 +112,11 @@ void __init ls1x_clk_init(void) hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, DIV_APB); clk_hw_register_clkdev(hw, "apb_clk", NULL); - clk_hw_register_clkdev(hw, "ls1x_i2c", NULL); - clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL); - clk_hw_register_clkdev(hw, "ls1x_spi", NULL); - clk_hw_register_clkdev(hw, "ls1x_wdt", NULL); + clk_hw_register_clkdev(hw, "ls1x-ac97", NULL); + clk_hw_register_clkdev(hw, "ls1x-i2c", NULL); + clk_hw_register_clkdev(hw, "ls1x-nand", NULL); + clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL); + clk_hw_register_clkdev(hw, "ls1x-spi", NULL); + clk_hw_register_clkdev(hw, "ls1x-wdt", NULL); clk_hw_register_clkdev(hw, "serial8250", NULL); }